Editing Streaming SIMD Extensions (section)

== Registers ==
SSE originally added eight new 128-bit registers known as <code>XMM0</code> through <code>XMM7</code>. The [[AMD64]] extensions from AMD added a further eight registers <code>XMM8</code> through <code>XMM15</code>, and this extension is duplicated in the [[Intel 64]] architecture. There is also a new 32-bit control/status register, <code>MXCSR</code>. The registers <code>XMM8</code> through <code>XMM15</code> are accessible only in 64-bit operating mode.
 
[[Image:XMM registers.svg|right|220px]]

SSE used only a single data type for XMM registers:
* four 32-bit [[single-precision]] floating-point numbers

[[SSE2]] would later expand the usage of the XMM registers to include:
* two 64-bit [[double-precision]] floating-point numbers or
* two 64-bit integers or
* four 32-bit integers or
* eight 16-bit short integers or
* sixteen 8-bit bytes or characters.

Because these 128-bit registers are additional machine states that the [[operating system]] must preserve across [[context switch|task switches]], they are disabled by default until the operating system explicitly enables them. This means that the OS must know how to use the <code>FXSAVE</code> and <code>FXRSTOR</code> instructions, which is the extended pair of instructions that can save all [[x86]] and SSE register states at once. This support was quickly added to all major IA-32 operating systems.

The first CPU to support SSE, the [[Pentium III]], shared execution resources between SSE and the [[floating-point unit]] (FPU).<ref name="MPR=1999-03-08">{{cite journal|url=http://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/pentium3%20(mpr).pdf|author=Diefendorff, Keith|date=March 8, 1999|title=Pentium III = Pentium II + SSE: Internet SSE Architecture Boosts Multimedia Performance|journal=[[Microprocessor Report]]|volume=13|issue=3|access-date=September 1, 2017|archive-date=April 17, 2018|archive-url=https://web.archive.org/web/20180417203519/http://docencia.ac.upc.edu/ETSETB/SEGPAR/microprocessors/pentium3%20%28mpr%29.pdf|url-status=live}}</ref> While a [[compiled]] application can interleave FPU and SSE instructions side-by-side, the Pentium III will not issue an FPU and an SSE instruction in the same [[clock cycle]]. This limitation reduces the effectiveness of [[instruction pipeline|pipelining]], but the separate XMM registers do allow SIMD and scalar floating-point operations to be mixed without the performance hit from explicit MMX/floating-point mode switching.