Editing SystemC (section)

== Language specification ==
SystemC is defined and promoted by the Open SystemC Initiative (OSCI — now [[Accellera]]), and has been approved by the IEEE Standards Association as IEEE 1666-2011<ref>{{cite web|url=http://standards.ieee.org/getieee/1666/|archive-url=https://web.archive.org/web/20071221043422/http://standards.ieee.org/getieee/1666/|url-status=dead|archive-date=December 21, 2007|title=Browse Standards|website=[[IEEE]]}}</ref> - the SystemC Language Reference Manual (LRM). The LRM provides the definitive statement of the semantics of SystemC. OSCI also provide an open-source proof-of-concept simulator (sometimes incorrectly referred to as the reference simulator), which can be downloaded from the OSCI website.<ref>[http://www.systemc.org www.systemc.org, the Open SystemC Initiative website] {{Webarchive|url=https://web.archive.org/web/20081006172519/http://systemc.org/ |date=2008-10-06 }}</ref> Although it was the intent of OSCI that commercial vendors and academia could create original software compliant to IEEE 1666, in practice most SystemC implementations have been at least partly based on the OSCI proof-of-concept simulator.

=== Compared to HDLs ===
SystemC has semantic similarities to [[VHDL]] and [[Verilog]], but may be said to have a syntactical overhead compared to these when used as a [[hardware description language]]. On the other hand, it offers a greater range of expression, similar to [[Object-oriented programming|object-oriented design partitioning]] and template classes. Although strictly a C++ class library, SystemC is sometimes viewed as being a language in its own right. Source code can be compiled with the SystemC library (which includes a simulation kernel) to give an executable. The performance of the OSCI open-source implementation is typically worse than commercial VHDL/Verilog simulators when used for [[register transfer level]] simulation.{{Citation needed|date=December 2021}}

=== Versions ===
SystemC version 1 included common [[hardware description language|hardware-description language]] features such as structural hierarchy and connectivity, clock-cycle accuracy, delta cycles, [[four-valued logic]] (0, 1, X, Z), and bus-resolution functions.

SystemC version 2 onward focused on communication abstraction, [[transaction-level modeling]], and virtual-platform modeling. It also added abstract ports, dynamic processes, and timed event notifications.