Editing Tejas and Jayhawk (section)

==History==
In early 2003, Intel showed Tejas and a plan to release it sometime in 2004 with possible delays into 2005. Its development however, was cancelled on May 7, 2004.<ref>{{Cite web |date=2004-05-07 |title=Intel cancels Tejas, moves to dual-core designs |url=https://www.eetimes.com/intel-cancels-tejas-moves-to-dual-core-designs/ |website=EETimes}}</ref> Analysts attribute these issues to heat and power consumption problems due to Intel's goal of reaching ever higher clock speeds, at the detriment of work done per clock (and therefore performance per clock). This was already the case with Prescott and its mediocre performance increase over [[Pentium 4#Northwood|Northwood]] despite higher clock speeds, not to mention heavy competition from [[Advanced Micro Devices]] with their [[Athlon 64]]. Prescott was supposed to attain >5&nbsp;GHz speeds with ease, yet this was not possible due to physical limitations such as heat generated and power consumed at ambient temperatures (the "power wall"). Tejas went even further ahead with this paradigm, with Intel targeting 10&nbsp;GHz [[clock speed]]s by 2011 trying to fulfill the prediction made by [[Andrew  Grove]] in his keynote speech at the 1996 [[COMDEX|COMDEX/Fall]].<ref>{{Cite web |last=Grove |first=Andrew S |title=Intel Keynote Transcript |url=https://www.intel.com/pressroom/archive/speeches/ag111896.htm |access-date=2024-11-29 |website=www.intel.com}}</ref> Soon enough it was clear this represented a dead end.

This cancellation reflected Intel's intention to focus on dual-core chips for the [[Itanium]] platform. With respect to [[desktop computer|desktop]] processors, Intel's development efforts shifted to the [[Pentium M (microarchitecture)|Pentium M microarchitecture]] (itself a derivative of the [[P6 (microarchitecture)|P6 microarchitecture]] last used in the [[Pentium III]]) used in the [[Centrino]] notebook platform, which offered greatly improved performance per watt compared to Prescott and other [[NetBurst]] designs. The result of modernizing the P6 microarchitecture was the [[Intel Core|Core]] processor line, and later the [[Intel Core 2|Core 2]] line, offering Intel's first native dual core products for desktops and [[laptops]] while regaining the performance crown<ref>{{Cite web |last=Shimpi |first=Anand Lal |title=Intel's Core 2 Extreme & Core 2 Duo: The Empire Strikes Back |url=https://www.anandtech.com/show/2045 |access-date=2023-06-24 |website=www.anandtech.com}}</ref> back from AMD.

This defined the end for the NetBurst architecture, with Core setting the foundation and path for power efficient architectures that followed along the [[Tick–tock model]]. Although NetBurst was a dead end for the company, its concepts were later reused and repurposed<ref>{{Cite web |date=2022-06-17 |title=Intel's Netburst: Failure is a Foundation for Success |url=https://chipsandcheese.com/2022/06/17/intels-netburst-failure-is-a-foundation-for-success/ |access-date=2023-06-24 |website=Chips and Cheese |language=en-US}}</ref> in [[Sandy Bridge]].

To bridge the gap left by Tejas' cancellation in the x86 market, Intel did one last revision to NetBurst, codenamed [[Pentium 4#Cedar Mill|Cedar Mill]] (single core) and Presler (dual core).