Editing Translation lookaside buffer (section)

==Overview==
{{See also|CPU cache#Address_translation|l1=CPU cache § Address translation}}
[[File:Translation Lookaside Buffer.png|thumb|373x373px|General working of TLB<ref>{{Cite book|title=Operating Systems Concepts|url=https://archive.org/details/operatingsystemc00silb_391|url-access=registration|last=Silberschatz, Galvin, Gagne|first=Abraham, Peter B. , Greg|publisher=John Wiley & Sons. INC|year=2009|isbn=978-0-470-12872-5|location=United States of America}}</ref>]]
A TLB has a fixed number of slots containing [[page table|page-table]] entries and segment-table entries; page-table entries map virtual addresses to [[physical address]]es and intermediate-table addresses, while segment-table entries map virtual addresses to segment addresses, intermediate-table addresses and page-table addresses.  The [[virtual memory]] is the memory space as seen from a process; this space is often split into [[Page (computer memory)|pages]] of a fixed size (in paged memory), or less commonly into [[Segment (memory)|segments]] of variable sizes (in segmented memory). The page table, generally stored in [[main memory]], keeps track of where the virtual pages are stored in the physical memory. This method uses two memory accesses (one for the page-table entry, one for the byte) to access a byte. First, the page table is looked up for the frame number. Second, the frame number with the page offset gives the actual address. Thus, any straightforward virtual memory scheme would have the effect of doubling the memory access time. Hence, the TLB is used to reduce the time taken to access the memory locations in the page-table method. The TLB is a cache of the page table, representing only a subset of the page-table contents.

Referencing the physical memory addresses, a TLB may reside between the CPU and the [[CPU cache]], between the CPU cache and [[primary storage]] memory, or between levels of a multi-level cache.  The placement determines whether the cache uses physical or virtual addressing.  If the cache is virtually addressed, requests are sent directly from the CPU to the cache, and the TLB is accessed only on a [[cache miss]].  If the cache is physically addressed, the CPU does a TLB lookup on every memory operation, and the resulting physical address is sent to the cache.

In a [[Harvard architecture]] or [[modified Harvard architecture]], a separate virtual address space or memory-access hardware may exist for instructions and data.  This can lead to distinct TLBs for each access type, an ''instruction translation lookaside buffer'' (ITLB) and a ''data translation lookaside buffer'' (DTLB).  Various benefits have been demonstrated with separate data and instruction TLBs.<ref>{{cite journal |author1=Chen, J. Bradley |author2=Borg, Anita|author-link3=Norman Jouppi |author3=Jouppi, Norman P. |title=A Simulation Based Study of TLB Performance |journal=ACM SIGARCH Computer Architecture News |volume=20 |issue=2 |year=1992 |pages=114–123 |doi=10.1145/146628.139708|doi-access=free }}</ref>

The TLB can be used as a fast lookup hardware cache. The figure shows the working of a TLB. Each entry in the TLB consists of two parts: a tag and a value. If the tag of the incoming virtual address matches the tag in the TLB, the corresponding value is returned. Since the TLB lookup is usually a part of the instruction pipeline, searches are fast and cause essentially no performance penalty.  However, to be able to search within the instruction pipeline, the TLB has to be small.

A common optimization for physically addressed caches is to perform the TLB lookup in parallel with the cache access. Upon each virtual memory reference, the hardware checks the TLB to see whether the page number is held therein. If yes, it is a TLB hit, and the translation is made. The frame number is returned and is used to access the memory. If the page number is not in the TLB, the page table must be checked. Depending on the CPU, this can be done automatically in hardware or using an interrupt to the operating system. When the frame number is obtained, it can be used to access the memory. In addition, we add the page number and frame number to the TLB, so that they will be found quickly on the next reference. If the TLB is already full, a suitable block must be selected for replacement. There are different replacement methods like ''least recently used'' (LRU), ''first in, first out'' (FIFO) etc.; see the [[CPU cache#Address translation|address translation]] section in the cache article for more details about virtual addressing as it pertains to caches and TLBs.