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Unibus
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==Technical specifications== [[File:Unibus cable.jpg|thumb|A Unibus connector and extension cable]] The Unibus consists of 72 signals, usually connected via two 36-way [[edge connector]]s on each [[printed circuit board]]. When not counting the power and ground lines, it is usually referred to as a 56-line bus. It can exist within a [[backplane]] or on a cable. Up to 20 nodes (devices) can be connected to a single Unibus segment; additional segments can be connected via a bus [[repeater]]. The bus is completely [[asynchronous circuit|asynchronous]], allowing a mixture of fast and slow devices. It allows the overlapping of arbitration (selection of the next ''bus master'') while the current bus master is still performing data transfers. The 18 address lines allow the addressing of a maximum of 256 KB. Typically, the top 8 KB is reserved for the registers of the [[memory-mapped I/O]] devices used in the PDP-11 architecture. The design deliberately minimizes the amount of redundant logic required in the system. For example, a system always contains more slave devices than master devices so most of the complex logic required to implement asynchronous data transfers is forced into the relatively few master devices. For interrupts, only the ''interrupt-fielding processor'' needs to contain the complex timing logic. The result is that most I/O controllers can be implemented with simple logic, and most of the critical logic is implemented as a custom [[integrated circuit#SSI.2C MSI and LSI|MSI IC]].
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