Editing VHDL (section)

==History==
In 1983, VHDL was originally developed at the behest of the [[U.S. Department of Defense]] in order to document the behavior of the [[Application-specific integrated circuit|ASICs]] that supplier companies were including in equipment. The standard MIL-STD-454N<ref name="mil454n">{{cite book |title= Military Standard, Standard general requirements for electronic equipment |year = 1992 |author= Department of Defense |url=http://everyspec.com/MIL-STD/MIL-STD-0300-0499/MIL-STD-454N_9160/ |access-date=November 15, 2017}}</ref> in Requirement 64 in section 4.5.1 "ASIC documentation in VHDL" explicitly requires documentation of "Microelectronic Devices" in VHDL.

The idea of being able to simulate the ASICs from the information in this documentation was so obviously attractive that [[Logic simulation|logic simulators]] were developed that could read the VHDL files. The next step was the development of [[logic synthesis]] tools that read the VHDL and output a definition of the physical implementation of the circuit.

Due to the Department of Defense requiring as much of the syntax as possible to be based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in the development of Ada,{{citation needed|date=November 2010}} VHDL borrows heavily from the [[Ada (programming language)|Ada programming language]] in both concept and [[syntax]].

The initial version of VHDL, designed to [[IEEE]] standard IEEE 1076–1987,<ref name="originalversion">{{Cite book| title = 1076-1987 – IEEE Standard VHDL Language Reference Manual| doi = 10.1109/IEEESTD.1988.122645| year = 1988| isbn = 0-7381-4324-3}}</ref> included a wide range of data types, including numerical ([[integer]] and [[real data type|real]]), logical ([[bit]] and [[Boolean data type|Boolean]]), [[character (computing)|character]] and [[time]], plus [[Array data type|arrays]] of <code>bit</code> called <code>bit_vector</code> and of <code>character</code> called [[string (computer science)|string]].

A problem not solved by this edition, however, was "multi-valued logic", where a signal's [[drive strength]] (none, weak or strong) and unknown values are also considered. This required [[IEEE 1164|IEEE standard 1164]], which defined the 9-value logic types: scalar <code>std_logic</code> and its vector version <code>std_logic_vector</code>. Being a resolved subtype of its <code>std_Ulogic</code> parent type, <code>std_logic</code>-typed signals allow multiple driving for modeling bus structures, whereby the connected resolution function handles conflicting assignments adequately.

The updated [[IEEE 1076]], in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the <code>character</code> type to allow [[ISO-8859-1]] printable characters, added the <code>xnor</code> operator, etc.{{specify|date=November 2010}}

Minor changes in the standard (2000 and 2002) added the idea of protected types (similar to the concept of class in [[C++]]) and removed some restrictions from port mapping rules.

In addition to IEEE standard 1164, several child standards were introduced to extend functionality of the language. IEEE standard 1076.2 added better handling of real and complex data types. IEEE standard 1076.3 introduced [[Signedness|signed and unsigned]] types to facilitate arithmetical operations on vectors. IEEE standard 1076.1 (known as [[VHDL-AMS]]) provided analog and mixed-signal circuit design extensions.

Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative Towards ASIC Libraries) and [[microwave]] circuit design extensions.

In June 2006, the VHDL Technical Committee of [[Accellera]] (delegated by IEEE to work on the next update of the standard) approved so-called Draft 3.0 of VHDL-2006. While maintaining full compatibility with older versions, this proposed standard provides numerous extensions that make writing and managing VHDL code easier. Key changes include incorporation of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators, more flexible syntax of ''case'' and ''generate'' statements, incorporation of VHPI (VHDL Procedural Interface) (interface to C/C++ languages) and a subset of PSL ([[Property Specification Language]]). These changes should improve quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of VHDL for system-level descriptions.

In February 2008, Accellera approved VHDL 4.0, also informally known as VHDL 2008, which addressed more than 90 issues discovered during the trial period for version 3.0 and includes enhanced generic types. In 2008, Accellera released VHDL 4.0 to the IEEE for balloting for inclusion in IEEE 1076–2008. The VHDL standard IEEE 1076-2008<ref>{{Cite book |title = 1076-2008 – IEEE Standard VHDL Language Reference Manual |doi = 10.1109/IEEESTD.2009.4772740 |year = 2009 |isbn = 978-0-7381-6854-8}}</ref> was published in January 2009.

===Standardization===
The [[IEEE]] Standard 1076 defines the [[VHSIC]] [[Hardware Description Language]], or VHDL. It was originally developed under contract F33615-83-C-1003 from the [[United States Air Force]] awarded in 1983 to a team of Intermetrics, Inc. as language experts and prime contractor, [[Texas Instruments]] as chip design experts and [[IBM]] as computer-system design experts. The language has undergone numerous revisions and has a variety of sub-standards associated with it that augment or extend it in important ways.

IEEE Standard 1076 was and continues to be a milestone in the design of electronic systems.<ref>[https://ieee-p1076.gitlab.io/ IEEE P1076 Working Group VHDL Analysis and Standardization Group (VASG)]</ref>

====Revisions====
* IEEE 1076–1987<ref name="originalversion" /> First standardized revision of ver 7.2 of the language from the United States Air Force.
* IEEE 1076–1993<ref>{{Cite book |title = 1076-1993 – IEEE Standard VHDL Language Reference Manual |doi = 10.1109/IEEESTD.1994.121433 |year = 1994 |isbn = 0-7381-0986-X}}</ref> (also published with {{ISBN|1-55937-376-8}}). Significant improvements resulting from several years of feedback. Probably the most widely used version with the greatest vendor tool support.
* IEEE 1076–2000.<ref>{{Cite book |title = 1076-2000 – IEEE Standard VHDL Language Reference Manual |doi = 10.1109/IEEESTD.2000.92297 |year = 2000 |isbn = 0-7381-1948-2}}</ref> Minor revision. Introduces the use of ''protected types''.
* IEEE 1076–2002.<ref>{{Cite book |title = 1076-2002 – IEEE Standard VHDL Language Reference Manual |doi = 10.1109/IEEESTD.2002.93614 |year = 2002 |isbn = 0-7381-3247-0}}</ref> Minor revision of 1076–2000. Rules with regard to ''buffer ports'' are relaxed.
** IEC 61691-1-1:2004.<ref>{{Cite book |doi = 10.1109/IEEESTD.2004.95752 |title = IEC 61691-1-1 First edition 2004-10; IEEE 1076 — IEC/IEEE Behavioural Languages – Part 1-1: VHDL Language Reference Manual (Adoption of IEEE Std 1076-2002) |year = 2004 |isbn = 2-8318-7691-5}}</ref> IEC adoption of IEEE 1076–2002.
* IEEE 1076c–2007.<ref>{{Cite book |title = 1076c-2007 – IEEE Standard VHDL Language Reference Manual Amendment 1: Procedural Language Application Interface |doi = 10.1109/IEEESTD.2007.4299594 |year = 2007 |isbn = 978-0-7381-5523-4}}</ref> Introduced VHPI, the VHDL procedural interface, which  provides software with the means to access the VHDL model. The VHDL language required minor modifications to accommodate the VHPI.
* IEEE 1076–2008 (previously referred to as 1076–200x). Major revision released on 2009-01-26. Among other changes, this standard incorporates a basic subset of PSL, allows for generics on packages and subprograms and introduces the use of ''external names''.
** IEC 61691-1-1:2011.<ref>{{Cite book |doi = 10.1109/IEEESTD.2011.5967868 |title = 61691-1-1-2011 — Behavioural languages – Part 1-1: VHDL Language Reference Manual |year = 2011 |isbn = 978-0-7381-6605-6}}</ref> IEC adoption of IEEE 1076–2008.
* IEEE 1076–2019. Major revision.

====Related standards====
* IEEE 1076.1 VHDL Analog and Mixed-Signal ([[VHDL-AMS]])
* IEEE 1076.1.1 VHDL-AMS Standard Packages (stdpkgs)
* IEEE 1076.2 VHDL Math Package
* IEEE 1076.3 VHDL Synthesis Package (vhdlsynth) ([[numeric std]])
* IEEE 1076.3 VHDL Synthesis Package – Floating Point (fphdl)
* IEEE 1076.4 Timing (VHDL Initiative Towards ASIC Libraries: vital)
* IEEE 1076.6 VHDL Synthesis Interoperability (withdrawn in 2010)<ref>{{Cite web|url=https://standards.ieee.org/ieee/1076.6/3466/|title = IEEE 1076.6-2004 - IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis}}</ref>
* [[IEEE 1164]] VHDL Multivalue Logic (std_logic_1164) Packages