Editing WinChip (section)

==Overview==
===Design===
The design of the WinChip was quite different from other processors of the time. Instead of a large [[gate count]] and [[die (integrated circuit)|die]] area, IDT, using its experience from the [[RISC]] processor market, created a small and electrically efficient processor similar to the [[Intel 80486|80486]], because of its single [[Pipeline (computing)|pipeline]] and [[Out of Order execution#In-order processors|in-order execution]] [[microarchitecture]]. It was of much simpler design than its Socket 7 competitors, such as [[AMD K5]]/[[AMD K6|K6]], which were [[superscalar]] and based on dynamic translation to buffered [[micro-operation]]s with advanced instruction reordering ([[Out of Order execution|out of order execution]]).

===Use===
WinChip was, in general, designed to perform well with popular applications that did few floating point calculations, if any. This included [[operating system]]s of the time and the majority of software used in businesses. It was also designed to be a drop-in replacement for the more complex, and thus more expensive, processors it was competing with. This allowed IDT/Centaur to take advantage of an established system platform (Intel's [[Socket 7]]).

===Later developments===
WinChip 2, an update of C6, retained the simple in-order execution pipeline of its predecessor, but added dual MMX/3DNow! processing units that could operate in superscalar execution.<ref name="WinChip2DataSheet" /> This made it the only non-AMD CPU on Socket 7 to support 3DNow! instructions. WinChip 2A added [[CPU multiplier|fractional multiplier]]s and adopted a 100&nbsp;MHz [[front side bus]] to improve memory access and L2 cache performance.<ref>{{cite web |last=Hare |first=Chris |url=http://users.erols.com/chare/cpuspeed.htm |title=Processor Speed Settings |accessdate=24 April 2007 |url-status=dead |archiveurl=https://web.archive.org/web/20070428051306/http://users.erols.com/chare/cpuspeed.htm |archivedate=28 April 2007 }}</ref> It also adopted a [[PR rating|performance rating]] nomenclature instead of reporting the real clock speed, similar to contemporary AMD and [[Cyrix]] processors.

Another revision, the WinChip 2B, was also planned. This featured a die shrink to 0.25 μm, but was only shipped in limited numbers.<ref name=WinChipSandpile>{{cite web |url=http://www.sandpile.org/impl/c2.htm |title=IA-32 implementation: Centaur WinChip 2 |work=SandPile.org |accessdate=29 April 2007 |url-status=dead |archiveurl=https://web.archive.org/web/20070427100243/http://sandpile.org/impl/c2.htm |archivedate=27 April 2007 }}</ref>

A third model, the WinChip 3, was planned as well. This was meant to receive a doubled L1 cache, but the W3 CPU never made it to market.<ref name=WinChipSandpile />

===Performance===
Although the small die size and low power-usage made the processor notably inexpensive to manufacture, it never gained much market share. WinChip C6 was a competitor to the [[Intel P5|Intel Pentium]] and [[Pentium MMX]], [[Cyrix 6x86]], and AMD K5/K6. It performed adequately, but only in applications that used little [[floating point]] math. Its floating point performance was simply well below that of the Pentium and K6, being even slower than the Cyrix 6x86.<ref>{{cite web |last=Pabst |first=Thomas |url=http://www.tomshardware.com/1997/10/09/the_idt_winchip_c6_cpu/ |title=The IDT WinChip C6 CPU |work=Tom's Hardware |date=9 October 1997 |accessdate=29 April 2007}}</ref>