Editing Zilog Z8000 (section)

==History==
===Z80===
In the early 1970s, [[Intel]]'s management saw the [[microprocessor]] not so much as a product on its own, but as a way to create demand for their other products like [[static RAM]] and [[ROM]]. A reorganization in early 1974 further diluted the role of the microprocessor in the company. The designer of the [[Intel 4004]] and [[Intel 8080]], [[Federico Faggin]], decided to leave the company and start one dedicated to microprocessor design. Faggin left on 31 October 1974, joined by [[Ralph Ungermann]] and, later, the logic designer [[Masatoshi Shima]].{{sfn|Slater|2007|pp=2-3}}

Initially working on a concept for a simple [[microcontroller]], Faggin eventually concluded that the economics of the industry demanded that they introduce a product at the high-end, not the low-end. This led to a new concept initially known as the "Super 80", but eventually emerging as the [[Zilog Z80]]. The Z80 was a significant advance on the 8080, running on a single +5V power supply and adding several nice features from the [[Motorola 6800]]. Released in 1976, it was soon a huge hit.{{sfn|Slater|2007|p=4}}

===16-bit design===
While Shima was still working on the Z80 layout, Faggin began considering its future replacement by a 16-bit design, with the goal of being the first company to bring a new 16-bit single-chip design to market.{{efn|Several multi-chip 16-bit microprocessors existed by this point, but they were all based on existing [[minicomputer]] designs and were generally too expensive for general use. Single-chip versions of these emerged, but they remained expensive.{{sfn|Slater|2007|pp=4,5}}}} He felt that expanding the Z80 to 16-bits was not appropriate, the larger [[computer word]] size meant that many more features could be offered in the [[instruction set]] and the deliberately simple instructions of earlier designs would lead to chips that would be outperformed by freshly-designed 16-bit designs.{{sfn|Slater|2007|pp=2,3}}

In January 1976, Faggin hired Bernard Peuto, formerly of [[Amdahl Corporation]]. Peuto had previously studied and published extensively on the topic of word length, instruction sets and code density. The initial meetings on the concept were held at the end of March, at which time Faggin told Peuto he wanted the architecture completed in three months. The instruction set was delivered on time, but then it was time to turn that into a complete design.{{sfn|Slater|2007|p=3}} Peuto's design included the ability to work with 8-, 16- and 32-bit data, flexible addressing modes, and dedicated coprocessor support.{{sfn|Slater|2007|p=6}}

It was during this time that Ungermann explained the economics of the chip industry to Peuto, which were strongly influenced by the size of the chip. At the time, most processors used 40-pin [[dual in-line package]]s (DIPs), but some used 28-pin packages for lower-cost systems, while others were using 48 or 64-pin packages for more powerful systems like minicomputers. The need to balance cost and power ultimately led to the idea of having two versions of the chip, the Z8001 with 23 [[address bus]] pins in a 48-pin chip, and the Z8002 with 16 address pins in a 40-pin chip.{{sfn|Slater|2007|p=6}}

In order to have a single instruction set that could be used on either design, they made the decision to use [[segmented memory]].{{sfn|Slater|2007|p=6}} In this concept, the basic instruction set uses 16-bit addresses, which could then be run on either version of the chip. To access larger amounts of memory, a separate set of instructions could set a 7-bit "segment number". On the 23-pin versions, the 7-bit segment number was sent out at the same time as the 16-bit base address, creating a single 23-bit address. This early design choice would ultimately have a profound effect on the desirability of the Z8000 series.{{sfn|Slater|2007|p=7}}

Shima would be responsible for turning the conceptual design into a physical one, and with the basic design completed, Shima first began considering it on 11 June 1976. At the time the system was to have eight 16-bit registers, and Shima began laying out such a design. But very late in the process the design team concluded that it needed more, and when they asked in October, Shima stated he had laid it out with enough room left over that they could double the number of registers.{{sfn|Slater|2007|p=9}}

===Introduction===
In June 1978, while Shima was still working on the design of the Z8000, Intel introduced the [[Intel 8086]]. Zilog had missed its chance to be the first company with a new, dedicated 16-bit design. In some ways the 8086 was similar to the Z8000, including the use of segmented memory, but in general it was a less advanced design with fewer [[processor register]]s and a much smaller maximum memory of 1&nbsp;[[megabyte]] rather than the 8000's 8&nbsp;MB.{{sfn|Slater|2007|p=9}}

It was not until early 1979 that production samples of the Z8000 were released. Zilog stated that the Z8001 and Z8002 were merely differently packaged versions of the same Z8000 chip, "the difference being achieved by a bonding option during manufacture".<ref name="pcw198107_zilog">{{ cite magazine | url=https://archive.org/details/PersonalComputerWorld1981-07/page/62/mode/2up | title=Zilog writes | magazine=Personal Computer World | last1=Pittman | first1=Phil | date=July 1981 | access-date=13 May 2024 | pages=62–63 }}</ref>

Even with 48 pins, there were not enough connections to allow for a complete 16-bit data bus and 24-bit address bus, as that would leave only 8 free pins, which is not nearly enough for various other interfacing needs like power, clocks and interrupts. To address this, the Z8001 multiplexed the address and data pins together. The first 16 pins of the 23-pin address bus were used on alternate cycles as a 16-bit data bus. This meant that every memory access took two complete memory cycles: first the address would be presented and had to be "latched" using external circuity, and then on the next cycle 16 bit of data would be read or written using the same pins.<ref>{{cite tech report |url=https://html.alldatasheet.net/html-pdf/1283758/ZILOG/Z8000/172/1/Z8000.html |title=Z8000}}</ref> This means the Z8000 would run roughly half as fast as something like the 68000, which had separate 16 data pins and 24 address pins on a larger 64-pin chip.{{Dubious|1=Multiplexed bus|reason=Multiplexed address/data bus does not necessarily slow down accesses. The address must be presented some time before the data can be read or written. The moment the address appears, the data bus is idle on most processors including the 68000.|date=March 2025}}

Zilog already had a strategy to deal with this problem, the Zilog 8010 memory controller. The 8010 automatically folded the 7 and 16-bit parts of the address back together into a single 23-bit address, as well as offering a number of memory mapping features that made it useful for supporting [[Computer multitasking|multitasking]] and [[virtual memory]]. However, the 8010 was not ready when the 8001 was introduced. This meant that for 18 months, Intel had a single-chip solution that could access 1&nbsp;MB, while the 8000 series was still practically limited to 64&nbsp;kB. The 8010 was eventually released almost a year later, and even then it required two chips to do what the 8086 did with one.{{sfn|Slater|2007|pp=7,8}}

The delays with the 8010 was particularly hurtful. In September 1979, [[Motorola]] introduced the [[Motorola 68000]], which had a complete 24-bit address bus, which allowed it to access up to 16&nbsp;MB without segmentation. It also offered all of the features Zilog advertised as being more advanced than the 8086, such as more registers and a wide set of addressing modes. The market generally chose Intel for lower-end offerings and the 68000 for the high-end. Shima left the company to return to Japan in 1980, and Faggin left shortly thereafter.{{sfn|Slater|2007|p=23}}

===Later versions===
The series was later expanded to include the Z8003 and Z8004 updated versions of the Z8001 and Z8002, respectively. These versions were designed to provide improved support for [[virtual memory]], adding new status registers to indicate [[segmentation fault]]s (test and set) and provide an abort capability.