Editing Zilog eZ80 (section)

== Design ==
{| class="infobox" style="font-size:88%;"
|-
|+ Zilog eZ80 registers in ADL mode
|-
|
{| style="font-size:88%;"
|-
| style="width:10px; text-align:center;"| <sup>2</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>2</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>2</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>2</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto;" | ''(bit&nbsp;position)''
|-
|colspan="17" | '''Main registers'''
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="8"| 0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="8"| Accumulator&nbsp;(A)
| style="text-align:center;background:#DDD" colspan="8"| Flags&nbsp;(F)
| style="background:white; color:black;"| '''AF'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| BCU
| style="text-align:center;" colspan="8"| B
| style="text-align:center;" colspan="8"| C
| style="background:white; color:black;"| '''BC'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| DEU
| style="text-align:center;" colspan="8"| D
| style="text-align:center;" colspan="8"| E
| style="background:white; color:black;"| '''DE'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| HLU
| style="text-align:center;" colspan="8"| H
| style="text-align:center;" colspan="8"| L
| style="background:white; color:black;"| '''HL'''
|-
|colspan="17" | '''Alternate (shadow) registers'''
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="8"| 0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="8"| Accumulator'&nbsp;(A')
| style="text-align:center;background:#DDD" colspan="8"| Flags'&nbsp;(F')
| style="background:white; color:black;"| '''AF{{'}}'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| BCU'
| style="text-align:center;" colspan="8"| B'
| style="text-align:center;" colspan="8"| C'
| style="background:white; color:black;"| '''BC{{'}}'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| DEU'
| style="text-align:center;" colspan="8"| D'
| style="text-align:center;" colspan="8"| E'
| style="background:white; color:black;"| '''DE{{'}}'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| HLU'
| style="text-align:center;" colspan="8"| H'
| style="text-align:center;" colspan="8"| L'
| style="background:white; color:black;"| '''HL{{'}}'''
|-
|colspan="17" | '''Index registers'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| IXU
| style="text-align:center;" colspan="8"| IXH
| style="text-align:center;" colspan="8"| IXL
| style="background:white; color:black;"| '''IX'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| IYU
| style="text-align:center;" colspan="8"| IYH
| style="text-align:center;" colspan="8"| IYL
| style="background:white; color:black;"| '''IY'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="24"| Stack Pointer
| style="background:white; color:black;"| '''SPL'''
|-
|colspan="17" | '''Other registers'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| Interrupt vector (base)
| style="text-align:center;background:#DDD" colspan="8"| 0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0&nbsp;0
| style="background:white; color:black;"| '''I'''
|- style="background:silver;color:black"
| style="background:white; color:black;" colspan="16"| &nbsp;
| style="text-align:center;" colspan="8"| Memory base
| style="background:white; color:black;"| '''MBASE'''
|- style="background:silver;color:black"
| style="background:white; color:black;" colspan="16"| &nbsp;
| style="text-align:center;" colspan="1"|
| style="text-align:center;" colspan="7"| Refresh counter
| style="background:white; color:black;"| '''R'''
|-
|colspan="17" | '''Program counter'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="24"| Program Counter
| style="background:white; color:black;"| '''PC'''
|-
|colspan="17" | '''Status flags'''
|- style="background:silver;color:black"
| style="background:white; color:black;" colspan="16"| &nbsp;
| style="text-align:center;"| [[Sign flag|S]]
| style="text-align:center;"| [[Zero flag|Z]]
| style="text-align:center;"| -
| style="text-align:center;"| [[Adjust flag|H]]
| style="text-align:center;"| -
| style="text-align:center;"| <sup>[[Parity flag|P]]</sup>/<sub>[[Overflow flag|V]]</sub>
| style="text-align:center;"| N
| style="text-align:center;"| [[Carry flag|C]]
| style="background:white; color:black" | '''F'''lags
|-
|- style="background:silver;color:black"
| style="background:white; color:black;" colspan="12"| &nbsp;
| style="text-align:center;" colspan="3"| ADL
| style="text-align:center;" colspan="3"| EF1
| style="text-align:center;" colspan="3"| EF2
| style="text-align:center;" colspan="3"| MADL
| style="background:white; color:black" | Bit flags
|}
|}
The eZ80 has a three-stage pipeline: fetch, decode, and execute. When an instruction changes the [[program counter]], it flushes the instructions that the CPU is currently processing. Available at up to 50&nbsp;MHz (2004), the performance is comparable to a Z80 clocked at 150&nbsp;MHz if fast memory is used (i.e. no wait states for [[opcode]] fetches, for data, or for I/O) or even higher in some applications (a 16-bit addition is 11 times as fast as in the original). The original Z80-compatible 16-bit register configuration is supported. The eZ80 also supports direct continuous addressing of 16&nbsp;[[Megabyte|MB]] of memory without a [[memory management unit]], by extending most registers (HL, BC, DE, IX, IY, SP, and PC) from 16 to 24 bits. In order to do so, the CPU has a full 24-bit address mode called ADL mode. In ADL mode, all Z80 16-bit registers are extended to 24 bits with additional upper 8-bit registers. For example, the HL register pair is extended with an uppermost register called HLU. The resulting 24-bit multi-byte register is collectively accessed by its old name, HL. The upper registers cannot be accessed individually.<ref>{{cite book |title=eZ80 CPU User Manual |date=July 15, 2009 |publisher=Zilog |edition=15, April 2015 |url=http://www.zilog.com/docs/um0077.pdf |access-date=16 June 2024}}</ref>

The processor has a 24-bit ALU [[arithmetic logic unit]] and overlapped processing of several instructions (the three-stage pipeline) which are the two primary reasons for its speed. Unlike the older [[Z280]] and [[Z380]] it does not have (or need) a cache memory. Instead, it is intended to work with fast [[Static random-access memory|SRAM]] directly as main memory (as this had become much cheaper). Nor does it have the multiplexed bus of the Z280, making it as easy to work with (interface to) as the original Z80 and Z180, and equally predictable when it comes to exact execution times.

The chip has a [[Memory refresh#CPU-based refresh|memory interface]] that is similar to the original Z80, including the bus request/acknowledge pins, and adds four integrated chip selects. Versions are available with on-chip flash memory and on-chip zero wait-state SRAM (up to 256&nbsp;[[Kilobyte|KB]] flash memory and 16&nbsp;KB SRAM) but there are also external buses on all models.