Editing Addressing mode (section)

====CPUs that do not use sequential execution====
CPUs that do not use sequential execution with a program counter are extremely rare. In some CPUs, each instruction always specifies the address of next instruction. Such CPUs have an instruction pointer that holds that specified address; it is not a program counter because there is no provision for incrementing it. Such CPUs include some [[drum memory]] computers such as the [[IBM 650]], the [[SECD machine]], [[LGP-30#RPC 4000|Librascope RPC 4000]], and the RTX 32P.<ref>{{cite web|url = http://www.ece.cmu.edu/~koopman/stack_computers/sec5_3.html |title =Architecture of the RTX 32P|work = Stack Computers|first = Philip|last= Koopman|date= 1989}}</ref>

On processors implemented with [[Microcode#Horizontal microcode|horizontal microcode]], the microinstruction may contain the high order bits of the next instruction address.

Other computing architectures go much further, attempting to bypass the [[von Neumann architecture#Von Neumann bottleneck|von Neumann bottleneck]] using a variety of [[program counter#Consequences in machine architecture|alternatives to the program counter]].