Editing BIOS (section)

=== Boot environment ===
The environment for the boot program is very simple: the CPU is in real mode and the general-purpose and segment registers are undefined, except SS, SP, CS, and DL. CS:IP always points to physical address <code>0x07C00</code>. What values CS and IP actually have is not well defined. Some BIOSes use a CS:IP of <code>0x0000:0x7C00</code> while others may use <code>0x07C0:0x0000</code>.<ref>{{Cite journal |last=Akeljic |first=Bekir |date=2017-01-01 |title=BIOS BASIC INPUT/ OUTPUT SYSTEM BIOS FUNCTIONS AND MODIFICATIONS |url=https://www.academia.edu/38015589 |url-status=live |journal=BIOS|pages=12 |url-access=subscription |archive-url=https://web.archive.org/web/20220808223747/https://www.academia.edu/38015589/BIOS_BASIC_INPUT_OUTPUT_SYSTEM_BIOS_FUNCTIONS_AND_MODIFICATIONS |archive-date=2022-08-08 |access-date=2022-08-08 |via=INTERNATIONAL UNIVERSITY TRAVNIKFACULITY OF INFORMATION TECHNOLOGY TRAVNIKSOFTWARE PROGRAMMING}}</ref> Because boot programs are always loaded at this fixed address, there is no need for a boot program to be relocatable. DL may contain the drive number, as used with [[INT 13H|interrupt 13h]], of the boot device. SS:SP points to a valid stack that is presumably large enough to support hardware interrupts, but otherwise SS and SP are undefined. (A stack must be already set up in order for interrupts to be serviced, and interrupts must be enabled in order for the system timer-tick interrupt, which BIOS always uses at least to maintain the time-of-day count and which it initializes during POST, to be active and for the keyboard to work. The keyboard works even if the BIOS keyboard service is not called; keystrokes are received and placed in the 15-character type-ahead buffer maintained by BIOS.) The boot program must set up its own stack, because the size of the stack set up by BIOS is unknown and its location is likewise variable; although the boot program can investigate the default stack by examining SS:SP, it is easier and shorter to just unconditionally set up a new stack.<ref>{{Cite web |title=BIOS - CodeDocs |url=https://codedocs.org/what-is/bios |access-date=2022-08-08 |website=codedocs.org |language=en}}</ref>

At boot time, all BIOS services are available, and the memory below address <code>0x00400</code> contains the [[interrupt vector table]]. BIOS POST has initialized the system timers, interrupt controller(s), DMA controller(s), and other motherboard/chipset hardware as necessary to bring all BIOS services to ready status. DRAM refresh for all system DRAM in conventional memory and extended memory, but not necessarily expanded memory, has been set up and is running. The [[interrupt vector]]s corresponding to the BIOS interrupts have been set to point at the appropriate entry points in the BIOS, hardware interrupt vectors for devices initialized by the BIOS have been set to point to the BIOS-provided ISRs, and some other interrupts, including ones that BIOS generates for programs to hook, have been set to a default dummy ISR that immediately returns. The BIOS maintains a reserved block of system RAM at addresses <code>0x00400–0x004FF</code> with various parameters initialized during the POST. All memory at and above address <code>0x00500</code> can be used by the boot program; it may even overwrite itself.<ref>{{Cite web |title=Memory Layout and Memory Map |url=http://flint.cs.yale.edu/feng/cos/resources/BIOS/mem.htm |access-date=2022-08-08 |website=flint.cs.yale.edu}}</ref><ref>{{Cite journal |year=2020 |title=BIOS Data ACPI Table (BDAT) |url=https://uefi.org/sites/default/files/resources/BDAT%20Specification%20v4.0%20Draft5_0.pdf |url-status=live |journal=[[Interface Specification]] |volume=4 |issue=5 |pages=67 |archive-url=https://web.archive.org/web/20210703231310/https://uefi.org/sites/default/files/resources/BDAT%20Specification%20v4.0%20Draft5_0.pdf |archive-date=2021-07-03 |access-date=2022-08-08}}</ref>