Editing Canonical normal form (section)

===Design trade-offs considered in addition to canonical forms===
One might suppose that the work of designing an adder stage is now complete, but we haven't addressed the fact that all 3 of the input variables have to appear in both their direct and complement forms.  There's no difficulty about the addends ''x'' and ''y'' in this respect, because they are static throughout the addition and thus are normally held in latch circuits that routinely have both direct and complement outputs. (The simplest latch circuit made of NOR gates is a pair of gates cross-coupled to make a flip-flop: the output of each is wired as one of the inputs to the other.) There is also no need to create the complement form of the sum ''u''. However, the carry out of one bit position must be passed as the carry into the next bit position in both direct and complement forms.  The most straightforward way to do this is to pass ''co'' through a 1-input NOR gate and label the output ''co''&prime;, but that would add a gate delay in the worst possible place, slowing down the rippling of carries from right to left. An additional 4-input NOR gate building the canonical form of ''co''&prime; (out of the opposite minterms as ''co'') solves this problem.

: <math>co'(ci, x, y) = \mathrm{AND}(M_3,M_5,M_6,M_7) = \mathrm{NOR}(m_3,m_5,m_6,m_7).</math>
{| style="margin: 1em auto 1em auto"
|+ '''Truth tables'''
|
{| class="wikitable" style="margin: 1em auto 1em auto"
!width="50"|ci
!width="50"|x
!width="50"|y
!width="50"|M<sub>3</sub>
!width="50"|M<sub>5</sub>
!width="50"|M<sub>6</sub>
!width="50"|M<sub>7</sub>
!width="50"|AND
!width="50"|co'(ci,x,y)
|-
|0||0||0||1||1||1||1||1||1
|-
|0||0||1||1||1||1||1||1||1
|-
|0||1||0||1||1||1||1||1||1
|-
|0||1||1||0||1||1||1||0||0
|-
|1||0||0||1||1||1||1||1||1
|-
|1||0||1||1||0||1||1||0||0
|-
|1||1||0||1||1||0||1||0||0
|-
|1||1||1||1||1||1||0||0||0
|}
|-
|
{| class="wikitable" style="margin: 1em auto 1em auto"
!width="50"|ci
!width="50"|x
!width="50"|y
!width="50"|m<sub>3</sub>
!width="50"|m<sub>5</sub>
!width="50"|m<sub>6</sub>
!width="50"|m<sub>7</sub>
!width="50"|NOR
!width="50"|co'(ci,x,y)
|-
|0||0||0||0||0||0||0||1||1
|-
|0||0||1||0||0||0||0||1||1
|-
|0||1||0||0||0||0||0||1||1
|-
|0||1||1||1||0||0||0||0||0
|-
|1||0||0||0||0||0||0||1||1
|-
|1||0||1||0||1||0||0||0||0
|-
|1||1||0||0||0||1||0||0||0
|-
|1||1||1||0||0||0||1||0||0
|}
|}
The trade-off to maintain full speed in this way includes an unexpected cost (in addition to having to use a bigger gate). If we'd just used that 1-input gate to complement ''co'', there would have been no use for the minterm <math>m_7</math>, and the gate that generated it could have been eliminated. Nevertheless, it is still a good trade.

Now we could have implemented those functions exactly according to their SoP and PoS canonical forms, by turning NOR gates into the functions specified.  A NOR gate is made into an OR gate by passing its output through a 1-input NOR gate; and it is made into an AND gate by passing each of its inputs through a 1-input NOR gate.  However, this approach not only increases the number of gates used, but also doubles the number of gate delays processing the signals, cutting the processing speed in half.  Consequently, whenever performance is vital, going beyond canonical forms and doing the Boolean algebra to make the unenhanced NOR gates do the job is well worthwhile.