Editing Cell (processor) (section)

====Bandwidth assessment====
At 3.2&nbsp;GHz, each channel flows at a rate of 25.6&nbsp;GB/s. Viewing the EIB in isolation from the system elements it connects, achieving twelve concurrent transactions at this flow rate works out to an abstract EIB bandwidth of 307.2&nbsp;GB/s. Based on this view many IBM publications depict available EIB bandwidth as "greater than 300&nbsp;GB/s". This number reflects the peak instantaneous EIB bandwidth scaled by processor frequency.<ref>{{Cite web |title=Cell Multiprocessor Communication Network: Built for Speed |url=http://hpc.pnl.gov/people/fabrizio/papers/ieeemicro-cell.pdf |url-status=dead |archive-url=https://web.archive.org/web/20070107202021/http://hpc.pnl.gov/people/fabrizio/papers/ieeemicro-cell.pdf |archive-date=January 7, 2007 |access-date=March 22, 2007 |publisher=IEEE}}</ref>

However, other technical restrictions are involved in the arbitration mechanism for packets accepted onto the bus. The IBM Systems Performance group explained:
{{blockquote|Each unit on the EIB can simultaneously send and receive 16 bytes of data every bus cycle. The maximum data bandwidth of the entire EIB is limited by the maximum rate at which addresses are snooped across all units in the system, which is one per bus cycle. Since each snooped address request can potentially transfer up to 128 bytes, the theoretical peak data bandwidth on the EIB at 3.2&nbsp;GHz is 128Bx1.6&nbsp;GHz {{=}} 204.8&nbsp;GB/s.<ref name="pacellperf" />}}

This quote apparently represents the full extent of IBM's public disclosure of this mechanism and its impact. The EIB arbitration unit, the snooping mechanism, and interrupt generation on segment or page translation faults are not well described in the documentation set as yet made public by IBM.{{Citation needed|date=June 2009}}

In practice, effective EIB bandwidth can also be limited by the ring participants involved. While each of the nine processing cores can sustain 25.6&nbsp;GB/s read and write concurrently, the memory interface controller (MIC) is tied to a pair of XDR memory channels permitting a maximum flow of 25.6&nbsp;GB/s for reads and writes combined and the two IO controllers are documented as supporting a peak combined input speed of 25.6&nbsp;GB/s and a peak combined output speed of 35&nbsp;GB/s.

To add further to the confusion, some older publications cite EIB bandwidth assuming a 4&nbsp;GHz system clock. This reference frame results in an instantaneous EIB bandwidth figure of 384&nbsp;GB/s and an arbitration-limited bandwidth figure of 256&nbsp;GB/s.

All things considered the theoretic 204.8&nbsp;GB/s number most often cited is the best one to bear in mind. The ''IBM Systems Performance'' group has demonstrated SPU-centric data flows achieving 197&nbsp;GB/s on a Cell processor running at 3.2&nbsp;GHz so this number is a fair reflection on practice as well.<ref name="pacellperf" />