Editing Central processing unit (section)

==Structure and implementation==
{{See also|Processor design}}
[[File:ABasicComputer.svg|thumb|upright=1.7|Block diagram of a basic uniprocessor-CPU computer. Black lines indicate data flow, whereas red lines indicate control flow; arrows indicate flow directions.]]

Hardwired into a CPU's circuitry is a set of basic operations it can perform, called an [[instruction set architecture|instruction set]]. Such operations may involve, for example, adding or subtracting two numbers, comparing two numbers, or jumping to a different part of a program. Each instruction is represented by a unique combination of [[bit]]s, known as the machine language [[opcode]]. While processing an instruction, the CPU decodes the opcode (via a [[binary decoder]]) into control signals, which orchestrate the behavior of the CPU. A complete machine language instruction consists of an opcode and, in many cases, additional bits that specify arguments for the operation (for example, the numbers to be summed in the case of an addition operation). Going up the complexity scale, a machine language program is a collection of machine language instructions that the CPU executes.

The actual mathematical operation for each instruction is performed by a [[combinational logic]] circuit within the CPU's processor known as the [[arithmetic–logic unit]] or ALU. In general, a CPU executes an instruction by fetching it from memory, using its ALU to perform an operation, and then storing the result to memory. Besides the instructions for integer mathematics and logic operations, various other machine instructions exist, such as those for loading data from memory and storing it back, branching operations, and mathematical operations on floating-point numbers performed by the CPU's [[floating-point unit]] (FPU).<ref>{{cite web |author=Wienand |first=Ian |date=September 3, 2013 |title=Computer Science from the Bottom Up, Chapter 3. Computer Architecture |url=http://www.bottomupcs.com/csbu.pdf#page=44 |url-status=live |archive-url=https://web.archive.org/web/20160206225834/http://www.bottomupcs.com/csbu.pdf#page=44 |archive-date=February 6, 2016 |access-date=January 7, 2015 |website=bottomupcs.com |format=PDF}}</ref>

===Control unit===
{{main|Control unit}}
The '''control unit''' (CU) is a component of the CPU that directs the operation of the processor. It tells the computer's memory, arithmetic and logic unit and input and output devices how to respond to the instructions that have been sent to the processor.

It directs the operation of the other units by providing timing and control signals. Most computer resources are managed by the CU. It directs the flow of data between the CPU and the other devices. [[John von Neumann]] included the control unit as part of the [[von Neumann architecture]]. In modern computer designs, the control unit is typically an internal part of the CPU with its overall role and operation unchanged since its introduction.<ref>{{Cite web|date=2018-09-24|title=Introduction of Control Unit and its Design|url=https://www.geeksforgeeks.org/introduction-of-control-unit-and-its-design/|access-date=2021-01-12|website=GeeksforGeeks|language=en-US|archive-date=2021-01-15|archive-url=https://web.archive.org/web/20210115072904/https://www.geeksforgeeks.org/introduction-of-control-unit-and-its-design/|url-status=live}}</ref>

===Arithmetic logic unit===
{{Main|Arithmetic logic unit}}
[[File:ALU block.gif|thumb|upright=1.3|Symbolic representation of an ALU and its input and output signals]]

The arithmetic logic unit (ALU) is a digital circuit within the processor that performs integer arithmetic and [[bitwise logic]] operations. The inputs to the ALU are the data words to be operated on (called [[operands]]), status information from previous operations, and a code from the control unit indicating which operation to perform. Depending on the instruction being executed, the operands may come from [[processor register|internal CPU registers]], external memory, or constants generated by the ALU itself.

When all input signals have settled and propagated through the ALU circuitry, the result of the performed operation appears at the ALU's outputs. The result consists of both a data word, which may be stored in a register or memory, and status information that is typically stored in a special, internal CPU register reserved for this purpose.

Modern CPUs typically contain more than one ALU to improve performance.

===Address generation unit===
{{Main|Address generation unit}}
The address generation unit (AGU), sometimes also called the address computation unit (ACU),<ref>{{cite web |last1=Van Berkel |first1=Cornelis |last2=Meuwissen |first2=Patrick |date=January 12, 2006 |title=Address generation unit for a processor (US 2006010255 A1 patent application) |url=https://patents.google.com/patent/US20060010255 |url-status=live |archive-url=https://web.archive.org/web/20160418074853/http://www.google.com/patents/US20060010255 |archive-date=April 18, 2016 |access-date=December 8, 2014 |website=google.com}} {{verify source|date=August 2019|reason=This ref was deleted ([[Special:Diff/897932214]]) by a bug in VisualEditor and later restored by a bot from the original cite at [[Special:Permalink/897793086]] cite #1 - please verify the cite's accuracy and remove this {verify source} template. [[User:GreenC bot/Job 18]]}}</ref> is an [[execution unit]] inside the CPU that calculates [[Memory address|addresses]] used by the CPU to access [[main memory]]. By having address calculations handled by separate circuitry that operates in parallel with the rest of the CPU, the number of [[CPU cycle]]s required for executing various [[machine instruction]]s can be reduced, bringing performance improvements.

While performing various operations, CPUs need to calculate memory addresses required for fetching data from the memory; for example, in-memory positions of [[array element]]s must be calculated before the CPU can fetch the data from actual memory locations. Those address-generation calculations involve different [[integer arithmetic operation]]s, such as addition, subtraction, [[modulo operation]]s, or [[bit shift]]s. Often, calculating a memory address involves more than one general-purpose machine instruction, which do not necessarily [[Instruction cycle|decode and execute]] quickly. By incorporating an AGU into a CPU design, together with introducing specialized instructions that use the AGU, various address-generation calculations can be offloaded from the rest of the CPU, and can often be executed quickly in a single CPU cycle.

Capabilities of an AGU depend on a particular CPU and its [[Computer architecture|architecture]]. Thus, some AGUs implement and expose more address-calculation operations, while some also include more advanced specialized instructions that can operate on multiple [[operand]]s at a time. Some CPU architectures include multiple AGUs so more than one address-calculation operation can be executed simultaneously, which brings further performance improvements due to the [[superscalar]] nature of advanced CPU designs. For example, [[Intel]] incorporates multiple AGUs into its [[Sandy Bridge (microarchitecture)|Sandy Bridge]] and [[Haswell (microarchitecture)|Haswell]] [[microarchitecture]]s, which increase bandwidth of the CPU memory subsystem by allowing multiple memory-access instructions to be executed in parallel.

===Memory management unit (MMU)===
{{Main|Memory management unit}}

Many microprocessors (in smartphones and desktop, laptop, server computers) have a memory management unit, translating logical addresses into physical RAM addresses, providing [[memory protection]] and [[paging]] abilities, useful for [[virtual memory]]. Simpler processors, especially [[microcontroller]]s, usually don't include an MMU.

===Cache===
A [[CPU cache]]<ref>{{cite web |author=Torres |first=Gabriel |date=September 12, 2007 |title=How The Cache Memory Works |url=https://hardwaresecrets.com/how-the-cache-memory-works/ |access-date=January 29, 2023 |website=Hardware Secrets}}</ref> is a [[hardware cache]] used by the central processing unit (CPU) of a [[computer]] to reduce the average cost (time or energy) to access [[Data (computing)|data]] from the [[main memory]]. A cache is a smaller, faster memory, closer to a [[processor core]], which stores copies of the data from frequently used main [[memory location]]s. Most CPUs have different independent caches, including [[Instruction cache|instruction]] and [[data cache]]s, where the data cache is usually organized as a hierarchy of several cache levels (L1, L2, L3, L4, etc.). Each ascending cache level is typically slower but larger than the preceding level with L1 being the fastest and the closest to the CPU.

All modern (fast) CPUs (with few specialized exceptions{{efn|A few specialized CPUs, accelerators or microcontrollers do not have a cache. To be fast, if needed/wanted, they still have an on-chip scratchpad memory that has a similar function, while software managed. In e.g. microcontrollers it can be better for hard real-time use, to have that or at least no cache, as with one level of memory latencies of loads are predictable.}}) have multiple levels of CPU caches. The first CPUs that used a cache had only one level of cache; unlike later level 1 caches, it was not split into L1d (for data) and L1i (for instructions). Almost all current CPUs with caches have a split L1 cache. They also have L2 caches and, for larger processors, L3 caches as well. The L2 cache is usually not split and acts as a common repository for the already split L1 cache. Every core of a [[multi-core processor]] has a dedicated L2 cache and is usually not shared between the cores. The L3 cache, and higher-level caches, are shared between the cores and are not split. An L4 cache is currently uncommon, and is generally on [[dynamic random-access memory]] (DRAM), rather than on [[static random-access memory]] (SRAM), on a separate die or chip. That was also the case historically with L1, while bigger chips have allowed integration of it and generally all cache levels, with the possible exception of the last level. Each extra level of cache tends to be bigger and is optimized differently.

Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the [[translation lookaside buffer]] (TLB) that is part of the [[memory management unit]] (MMU) that most CPUs have.

Caches are generally sized in powers of two: 2, 8, 16 etc. [[Kibibyte|KiB]] or [[Mebibyte|MiB]] (for larger non-L1) sizes, although the [[IBM z13 (microprocessor)|IBM z13]] has a 96 KiB L1 instruction cache.<ref>{{cite web|url=http://www.redbooks.ibm.com/redbooks/pdfs/sg248250.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.redbooks.ibm.com/redbooks/pdfs/sg248250.pdf |archive-date=2022-10-09 |url-status=live|title=IBM z13 and IBM z13s Technical Introduction|page=20|date=March 2016|publisher=[[IBM]]}} {{verify source |date=August 2019 |reason=This ref was deleted ([[Special:Diff/897933560]]) by a bug in VisualEditor and later restored by a bot from the original cite at [[Special:Permalink/895110016]] cite #3 – please verify the cite's accuracy and remove this {verify source} template. [[User:GreenC bot/Job 18]]}}</ref>

===Clock rate===
{{Main|Clock rate}}
Most CPUs are [[synchronous circuit]]s, which means they employ a [[clock signal]] to pace their sequential operations. The clock signal is produced by an external [[Electronic oscillator|oscillator circuit]] that generates a consistent number of pulses each second in the form of a periodic [[Square wave (waveform)|square wave]]. The frequency of the clock pulses determines the rate at which a CPU executes instructions and, consequently, the faster the clock, the more instructions the CPU will execute each second.

To ensure proper operation of the CPU, the clock period is longer than the maximum time needed for all signals to propagate (move) through the CPU. In setting the clock period to a value well above the worst-case [[propagation delay]], it is possible to design the entire CPU and the way it moves data around the "edges" of the rising and falling clock signal. This has the advantage of simplifying the CPU significantly, both from a design perspective and a component-count perspective. However, it also carries the disadvantage that the entire CPU must wait on its slowest elements, even though some portions of it are much faster. This limitation has largely been compensated for by various methods of increasing CPU parallelism (see below).

However, architectural improvements alone do not solve all of the drawbacks of globally synchronous CPUs. For example, a clock signal is subject to the delays of any other electrical signal. Higher clock rates in increasingly complex CPUs make it more difficult to keep the clock signal in phase (synchronized) throughout the entire unit. This has led many modern CPUs to require multiple identical clock signals to be provided to avoid delaying a single signal significantly enough to cause the CPU to malfunction. Another major issue, as clock rates increase dramatically, is the amount of heat that is [[CPU power dissipation|dissipated by the CPU]]. The constantly changing clock causes many components to switch regardless of whether they are being used at that time. In general, a component that is switching uses more energy than an element in a static state. Therefore, as clock rate increases, so does energy consumption, causing the CPU to require more [[heat dissipation]] in the form of [[CPU cooling]] solutions.

One method of dealing with the switching of unneeded components is called [[clock gating]], which involves turning off the clock signal to unneeded components (effectively disabling them). However, this is often regarded as difficult to implement and therefore does not see common usage outside of very low-power designs. One notable recent CPU design that uses extensive clock gating is the IBM [[PowerPC]]-based [[Xenon (processor)|Xenon]] used in the [[Xbox 360]]; this reduces the power requirements of the Xbox 360.<ref>{{cite web | last = Brown | first = Jeffery | title = Application-customized CPU design | publisher = IBM developerWorks | url = http://www-128.ibm.com/developerworks/power/library/pa-fpfxbox/?ca=dgr-lnxw07XBoxDesign | year = 2005 | access-date = 2005-12-17 | archive-url = https://web.archive.org/web/20060212002837/http://www-128.ibm.com/developerworks/power/library/pa-fpfxbox/?ca=dgr-lnxw07XBoxDesign | archive-date = 2006-02-12 | url-status = dead}}</ref>

===Clockless CPUs===
Another method of addressing some of the problems with a global clock signal is the removal of the clock signal altogether. While removing the global clock signal makes the design process considerably more complex in many ways, asynchronous (or clockless) designs carry marked advantages in power consumption and [[heat dissipation]] in comparison with similar synchronous designs. While somewhat uncommon, entire [[Asynchronous circuit#Asynchronous CPU|asynchronous CPUs]] have been built without using a global clock signal. Two notable examples of this are the [[ARM architecture family|ARM]] compliant [[AMULET microprocessor|AMULET]] and the [[MIPS architecture|MIPS]] R3000 compatible MiniMIPS.<ref name=":2">{{Cite journal |last1=Martin |first1=A. J. |last2=Nystrom |first2=M. |last3=Wong |first3=C. G. |date=November 2003 |title=Three generations of asynchronous microprocessors |url=https://ieeexplore.ieee.org/document/1246159 |url-status=live |journal=IEEE Design & Test of Computers |volume=20 |issue=6 |pages=9–17 |doi=10.1109/MDT.2003.1246159 |issn=0740-7475 |s2cid=15164301 |archive-url=https://web.archive.org/web/20211203174748/https://ieeexplore.ieee.org/document/1246159/ |archive-date=2021-12-03 |access-date=2022-01-05|url-access=subscription }}</ref>

Rather than totally removing the clock signal, some CPU designs allow certain portions of the device to be asynchronous, such as using asynchronous [[Arithmetic logic unit|ALUs]] in conjunction with superscalar pipelining to achieve some arithmetic performance gains. While it is not altogether clear whether totally asynchronous designs can perform at a comparable or better level than their synchronous counterparts, it is evident that they do at least excel in simpler math operations. This, combined with their excellent power consumption and heat dissipation properties, makes them very suitable for [[embedded computer]]s.<ref>{{cite conference |author1=Garside, J. D. |author2=Furber, S. B. |author3= Chung, S-H | title = AMULET3 Revealed | publisher = [[University of Manchester]] Computer Science Department | year = 1999 | url = http://www.cs.manchester.ac.uk/apt/publications/papers/async99_A3.php |book-title=Proceedings, Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems |doi=10.1109/ASYNC.1999.761522 | archive-url=https://web.archive.org/web/20051210205845/http://www.cs.manchester.ac.uk/apt/publications/papers/async99_A3.php | archive-date=December 10, 2005 | url-status=dead| url-access=subscription }}</ref>

===Voltage regulator module===
{{Main|Voltage regulator module}}
Many modern CPUs have a die-integrated power managing module which regulates on-demand voltage supply to the CPU circuitry allowing it to keep balance between performance and power consumption.

===Integer range===
Every CPU represents numerical values in a specific way. For example, some early digital computers represented numbers as familiar [[decimal]] (base 10) [[numeral system]] values, and others have employed more unusual representations such as [[bi-quinary coded decimal]] (base 2–5) or [[Balanced ternary|ternary]] (base 3). Nearly all modern CPUs represent numbers in [[Binary numeral system|binary]] form, with each digit being represented by some two-valued physical quantity such as a "high" or "low" [[volt]]age.{{Efn|The physical concept of [[voltage]] is an analog one by nature, practically having an infinite range of possible values. For the purpose of physical representation of binary numbers, two specific ranges of voltages are defined, one for logic '0' and another for logic '1'. These ranges are dictated by design considerations such as noise margins and characteristics of the devices used to create the CPU.}}

[[File:Binary Forty.PNG|thumb|left|A six-bit word containing the binary encoded representation of decimal value 40. Most modern CPUs employ word sizes that are a power of two, for example 8, 16, 32 or 64 bits.]]

Related to numeric representation is the size and precision of integer numbers that a CPU can represent. In the case of a binary CPU, this is measured by the number of bits (significant digits of a binary encoded integer) that the CPU can process in one operation, which is commonly called [[Word (data type)|''word size'']], ''bit width'', ''data path width'', ''integer precision'', or ''integer size''. A CPU's integer size determines the range of integer values on which it can directly operate.{{Efn|While a CPU's integer size sets a limit on integer ranges, this can (and often is) overcome using a combination of software and hardware techniques. By using additional memory, software can represent integers many magnitudes larger than the CPU can. Sometimes the CPU's [[instruction set architecture|instruction set]] will even facilitate operations on integers larger than it can natively represent by providing instructions to make large integer arithmetic relatively quick. This method of dealing with large integers is slower than utilizing a CPU with higher integer size, but is a reasonable trade-off in cases where natively supporting the full integer range needed would be cost-prohibitive. See [[Arbitrary-precision arithmetic]] for more details on purely software-supported arbitrary-sized integers.}} For example, an [[8-bit computing|8-bit]] CPU can directly manipulate integers represented by eight bits, which have a range of 256 (2<sup>8</sup>) discrete integer values.

Integer range can also affect the number of memory locations the CPU can directly address (an address is an integer value representing a specific memory location). For example, if a binary CPU uses 32 bits to represent a memory address then it can directly address 2<sup>32</sup> memory locations. To circumvent this limitation and for various other reasons, some CPUs use mechanisms (such as [[memory management unit|memory management]] or [[bank switching]]) that allow additional memory to be addressed.

CPUs with larger word sizes require more circuitry and consequently are physically larger, cost more and consume more power (and therefore generate more heat). As a result, smaller 4- or 8-bit [[microcontroller]]s are commonly used in modern applications even though CPUs with much larger word sizes (such as 16, 32, 64, even 128-bit) are available. When higher performance is required, however, the benefits of a larger word size (larger data ranges and address spaces) may outweigh the disadvantages. A CPU can have internal data paths shorter than the word size to reduce size and cost. For example, even though the [[IBM System/360]] [[instruction set architecture]] was a 32-bit instruction set, the System/360 [[IBM System/360 Model 30|Model 30]] and [[IBM System/360 Model 40|Model 40]] had 8-bit data paths in the arithmetic logical unit, so that a 32-bit add required four cycles, one for each 8 bits of the operands, and, even though the [[Motorola 68000 series]] instruction set was a 32-bit instruction set, the [[Motorola 68000]] and [[Motorola 68010]] had 16-bit data paths in the arithmetic logical unit, so that a 32-bit add required two cycles.

To gain some of the advantages afforded by both lower and higher bit lengths, many [[instruction set architecture|instruction sets]] have different bit widths for integer and floating-point data, allowing CPUs implementing that instruction set to have different bit widths for different portions of the device. For example, the IBM [[System/360]] instruction set was primarily 32 bit, but supported 64-bit [[floating-point arithmetic|floating-point]] values to facilitate greater accuracy and range in floating-point numbers.<ref name="amdahl1964" /> The System/360 Model 65 had an 8-bit adder for decimal and fixed-point binary arithmetic and a 60-bit adder for floating-point arithmetic.<ref>{{cite book|url=http://www.bitsavers.org/pdf/ibm/360/functional_characteristics/A22-6884-3_360-65_funcChar.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.bitsavers.org/pdf/ibm/360/functional_characteristics/A22-6884-3_360-65_funcChar.pdf |archive-date=2022-10-09 |url-status=live|title=IBM System/360 Model 65 Functional Characteristics|date=September 1968|publisher=[[IBM]]|pages=8–9|id=A22-6884-3}}</ref> Many later CPU designs use similar mixed bit width, especially when the processor is meant for general-purpose use where a reasonable balance of integer and floating-point capability is required.

===Parallelism===
{{Main|Parallel computing}}
[[File:Nopipeline.png|thumb|upright=2|Model of a subscalar CPU, in which it takes fifteen clock cycles to complete three instructions]]

The description of the basic operation of a CPU offered in the previous section describes the simplest form that a CPU can take. This type of CPU, usually referred to as ''subscalar'', operates on and executes one instruction on one or two pieces of data at a time, that is less than one [[Instructions per cycle|instruction per clock cycle]] ({{nowrap|IPC < 1}}).

This process gives rise to an inherent inefficiency in subscalar CPUs. Since only one instruction is executed at a time, the entire CPU must wait for that instruction to complete before proceeding to the next instruction. As a result, the subscalar CPU gets "hung up" on instructions which take more than one clock cycle to complete execution. Even adding a second [[execution unit]] (see below) does not improve performance much; rather than one pathway being hung up, now two pathways are hung up and the number of unused transistors is increased. This design, wherein the CPU's execution resources can operate on only one instruction at a time, can only possibly reach ''scalar'' performance (one instruction per clock cycle, {{nowrap|1=IPC = 1}}). However, the performance is nearly always subscalar (less than one instruction per clock cycle, {{nowrap|IPC < 1}}).

Attempts to achieve scalar and better performance have resulted in a variety of design methodologies that cause the CPU to behave less linearly and more in parallel. When referring to parallelism in CPUs, two terms are generally used to classify these design techniques:
* ''[[instruction-level parallelism]]'' (ILP), which seeks to increase the rate at which instructions are executed within a CPU (that is, to increase the use of on-die execution resources);
* ''[[task-level parallelism]]'' (TLP), which purposes to increase the number of [[Thread (computing)|threads]] or [[Process (computing)|processes]] that a CPU can execute simultaneously.

Each methodology differs both in the ways in which they are implemented, as well as the relative effectiveness they afford in increasing the CPU's performance for an application.{{Efn|Neither [[Instruction-level parallelism|ILP]] nor [[Task-level parallelism|TLP]] is inherently superior over the other; they are simply different means by which to increase CPU parallelism. As such, they both have advantages and disadvantages, which are often determined by the type of software that the processor is intended to run. High-TLP CPUs are often used in applications that lend themselves well to being split up into numerous smaller applications, so-called "[[embarrassingly parallel]] problems". Frequently, a computational problem that can be solved quickly with high TLP design strategies like [[symmetric multiprocessing]] takes significantly more time on high ILP devices like superscalar CPUs, and vice versa.}}

====Instruction-level parallelism====
{{Main|Instruction-level parallelism}}
[[File:Fivestagespipeline.png|thumb|left|upright=1.5|Basic five-stage pipeline. In the best case scenario, this pipeline can sustain a completion rate of one instruction per clock cycle.]]

One of the simplest methods for increased parallelism is to begin the first steps of instruction fetching and decoding before the prior instruction finishes executing. This is a technique known as [[instruction pipelining]], and is used in almost all modern general-purpose CPUs. Pipelining allows multiple instructions to be executed at a time by breaking the execution pathway into discrete stages. This separation can be compared to an assembly line, in which an instruction is made more complete at each stage until it exits the execution pipeline and is retired.

Pipelining does, however, introduce the possibility for a situation where the result of the previous operation is needed to complete the next operation; a condition often termed data dependency conflict. Therefore, pipelined processors must check for these sorts of conditions and delay a portion of the pipeline if necessary. A pipelined processor can become very nearly scalar, inhibited only by pipeline stalls (an instruction spending more than one clock cycle in a stage).

[[File:Superscalarpipeline.svg|thumb|upright=1.5|A simple superscalar pipeline. By fetching and dispatching two instructions at a time, a maximum of two instructions per clock cycle can be completed.]]

Improvements in instruction pipelining led to further decreases in the idle time of CPU components. Designs that are said to be superscalar include a long instruction pipeline and multiple identical [[execution unit]]s, such as [[load–store unit]]s, [[arithmetic–logic unit]]s, [[floating-point unit]]s and [[address generation unit]]s.<ref>{{cite web |last=Huynh |first=Jack |year=2003 |title=The AMD Athlon XP Processor with 512KB L2 Cache |url=http://courses.ece.uiuc.edu/ece512/Papers/Athlon.pdf |url-status=dead |archive-url=https://web.archive.org/web/20071128061217/http://courses.ece.uiuc.edu/ece512/Papers/Athlon.pdf |archive-date=2007-11-28 |access-date=2007-10-06 |publisher=University of Illinois |pages=6–11 |publication-place=Urbana–Champaign, Illinois}}</ref> In a superscalar pipeline, instructions are read and passed to a dispatcher, which decides whether or not the instructions can be executed in parallel (simultaneously). If so, they are dispatched to execution units, resulting in their simultaneous execution. In general, the number of instructions that a superscalar CPU will complete in a cycle is dependent on the number of instructions it is able to dispatch simultaneously to execution units.

Most of the difficulty in the design of a superscalar CPU architecture lies in creating an effective dispatcher. The dispatcher needs to be able to quickly determine whether instructions can be executed in parallel, as well as dispatch them in such a way as to keep as many execution units busy as possible. This requires that the instruction pipeline is filled as often as possible and requires significant amounts of [[CPU cache]]. It also makes [[Hazard (computer architecture)|hazard]]-avoiding techniques like [[branch prediction]], [[speculative execution]], [[register renaming]], [[out-of-order execution]] and [[transactional memory]] crucial to maintaining high levels of performance. By attempting to predict which branch (or path) a conditional instruction will take, the CPU can minimize the number of times that the entire pipeline must wait until a conditional instruction is completed. Speculative execution often provides modest performance increases by executing portions of code that may not be needed after a conditional operation completes. Out-of-order execution somewhat rearranges the order in which instructions are executed to reduce delays due to data dependencies. Also in case of [[Single instruction, multiple data|single instruction stream, multiple data stream]], a case when a lot of data from the same type has to be processed, modern processors can disable parts of the pipeline so that when a single instruction is executed many times, the CPU skips the fetch and decode phases and thus greatly increases performance on certain occasions, especially in highly monotonous program engines such as video creation software and photo processing.

When a fraction of the CPU is superscalar, the part that is not suffers a performance penalty due to scheduling stalls. The Intel [[P5 (microarchitecture)|P5]] [[Pentium]] had two superscalar ALUs which could accept one instruction per clock cycle each, but its FPU could not. Thus the P5 was integer superscalar but not floating point superscalar. Intel's successor to the P5 architecture, [[P6 (microarchitecture)|P6]], added superscalar abilities to its floating-point features.

Simple pipelining and superscalar design increase a CPU's ILP by allowing it to execute instructions at rates surpassing one instruction per clock cycle. Most modern CPU designs are at least somewhat superscalar, and nearly all general purpose CPUs designed in the last decade are superscalar. In later years some of the emphasis in designing high-ILP computers has been moved out of the CPU's hardware and into its software interface, or [[instruction set architecture]] (ISA). The strategy of the [[very long instruction word]] (VLIW) causes some ILP to become implied directly by the software, reducing the CPU's work in boosting ILP and thereby reducing design complexity.

====Task-level parallelism====
{{Main|Multithreading (computer architecture)|l1=Multithreading|Multi-core processor}}
Another strategy of achieving performance is to execute multiple [[Thread (computing)|threads]] or [[Process (computing)|processes]] in parallel. This area of research is known as [[parallel computing]].<ref>{{cite book |last1=Gottlieb |first1=Allan |url=http://dl.acm.org/citation.cfm?id=160438 |title=Highly parallel computing |last2=Almasi |first2=George S. |publisher=Benjamin/Cummings |year=1989 |isbn=978-0-8053-0177-9 |location=Redwood City, California |language=en-us |access-date=2016-04-25 |archive-url=https://web.archive.org/web/20181107043726/https://dl.acm.org/citation.cfm?id=160438 |archive-date=2018-11-07 |url-status=live}}</ref> In [[Flynn's taxonomy]], this strategy is known as [[Multiple instruction, multiple data|multiple instruction stream, multiple data stream]] (MIMD).<ref>{{Cite journal|last1=Flynn|first1=M. J. |s2cid=18573685 |author-link1=Michael J. Flynn|doi=10.1109/TC.1972.5009071|title=Some Computer Organizations and Their Effectiveness|journal=[[IEEE Transactions on Computers]]|volume=C-21|issue=9| pages=948–960| date=September 1972}}</ref>

One technology used for this purpose is [[multiprocessing]] (MP).<ref>{{cite journal |last1=Lu |first1=N.-P. |last2=Chung |first2=C.-P. |year=1998 |title=Parallelism exploitation in superscalar multiprocessing  |journal=IEE Proceedings - Computers and Digital Techniques |volume=145 |issue=4 |pages=255 |doi=10.1049/ip-cdt:19981955|doi-broken-date=7 December 2024 }}</ref> The initial type of this technology is known as [[symmetric multiprocessing]] (SMP), where a small number of CPUs share a coherent view of their memory system. In this scheme, each CPU has additional hardware to maintain a constantly up-to-date view of memory. By avoiding stale views of memory, the CPUs can cooperate on the same program and programs can migrate from one CPU to another. To increase the number of cooperating CPUs beyond a handful, schemes such as [[non-uniform memory access]] (NUMA) and [[directory-based coherence protocols]] were introduced in the 1990s. SMP systems are limited to a small number of CPUs while NUMA systems have been built with thousands of processors. Initially, multiprocessing was built using multiple discrete CPUs and boards to implement the interconnect between the processors. When the processors and their interconnect are all implemented on a single chip, the technology is known as chip-level multiprocessing (CMP) and the single chip as a [[multi-core processor]].

It was later recognized that finer-grain parallelism existed with a single program. A single program might have several threads (or functions) that could be executed separately or in parallel. Some of the earliest examples of this technology implemented [[input/output]] processing such as [[direct memory access]] as a separate thread from the computation thread. A more general approach to this technology was introduced in the 1970s when systems were designed to run multiple computation threads in parallel. This technology is known as [[Multithreading (computer architecture)|multi-threading]] (MT). The approach is considered more cost-effective than multiprocessing, as only a small number of components within a CPU are replicated to support MT as opposed to the entire CPU in the case of MP. In MT, the execution units and the memory system including the caches are shared among multiple threads. The downside of MT is that the hardware support for multithreading is more visible to software than that of MP and thus supervisor software like operating systems have to undergo larger changes to support MT. One type of MT that was implemented is known as [[temporal multithreading]], where one thread is executed until it is stalled waiting for data to return from external memory. In this scheme, the CPU would then quickly context switch to another thread which is ready to run, the switch often done in one CPU clock cycle, such as the [[UltraSPARC T1]]. Another type of MT is [[simultaneous multithreading]], where instructions from multiple threads are executed in parallel within one CPU clock cycle.

For several decades from the 1970s to early 2000s, the focus in designing high performance general purpose CPUs was largely on achieving high ILP through technologies such as pipelining, caches, superscalar execution, out-of-order execution, etc. This trend culminated in large, power-hungry CPUs such as the Intel [[Pentium 4]]. By the early 2000s, CPU designers were thwarted from achieving higher performance from ILP techniques due to the growing disparity between CPU operating frequencies and main memory operating frequencies as well as escalating CPU power dissipation owing to more esoteric ILP techniques.

CPU designers then borrowed ideas from commercial computing markets such as [[transaction processing]], where the aggregate performance of multiple programs, also known as [[throughput]] computing, was more important than the performance of a single thread or process.

This reversal of emphasis is evidenced by the proliferation of dual and more core processor designs and notably, Intel's newer designs resembling its less superscalar [[P6 (microarchitecture)|P6]] architecture. Late designs in several processor families feature chip-level multiprocessing, including the [[x86-64]] [[Opteron]] and [[Athlon 64 X2]], the [[SPARC]] [[UltraSPARC T1]], IBM [[POWER4]] and [[POWER5]], as well as several [[video game console]] CPUs like the [[Xbox 360]]'s triple-core PowerPC design, and the [[PlayStation 3]]'s 7-core [[Cell (microprocessor)|Cell microprocessor]].

====Data parallelism====
{{Main|Vector processor|SIMD}}
A less common but increasingly important paradigm of processors (and indeed, computing in general) deals with data parallelism. The processors discussed earlier are all referred to as some type of scalar device.{{Efn|Earlier the term ''scalar'' was used to compare the IPC count afforded by various ILP methods. Here the term is used in the strictly mathematical sense to contrast with vectors. See [[scalar (mathematics)]] and [[vector (geometric)]].}} As the name implies, vector processors deal with multiple pieces of data in the context of one instruction. This contrasts with scalar processors, which deal with one piece of data for every instruction. Using [[Flynn's taxonomy]], these two schemes of dealing with data are generally referred to as ''single instruction'' stream, ''multiple data'' stream ([[Single instruction, multiple data|SIMD]]) and ''single instruction'' stream, ''single data'' stream ([[Single instruction, single data|SISD]]), respectively. The great utility in creating processors that deal with vectors of data lies in optimizing tasks that tend to require the same operation (for example, a sum or a [[dot product]]) to be performed on a large set of data. Some classic examples of these types of tasks include [[multimedia]] applications (images, video and sound), as well as many types of [[Scientific computing|scientific]] and engineering tasks. Whereas a scalar processor must complete the entire process of fetching, decoding and executing each instruction and value in a set of data, a vector processor can perform a single operation on a comparatively large set of data with one instruction. This is only possible when the application tends to require many steps which apply one operation to a large set of data.

Most early vector processors, such as the [[Cray-1]], were associated almost exclusively with scientific research and [[cryptography]] applications. However, as multimedia has largely shifted to digital media, the need for some form of SIMD in general-purpose processors has become significant. Shortly after inclusion of [[floating-point unit]]s started to become commonplace in general-purpose processors, specifications for and implementations of SIMD execution units also began to appear for general-purpose processors in the mid-1990s. Some of these early SIMD specifications – like HP's [[Multimedia Acceleration eXtensions]] (MAX) and Intel's [[MMX (instruction set)|MMX]] – were integer-only. This proved to be a significant impediment for some software developers, since many of the applications that benefit from SIMD primarily deal with [[floating-point arithmetic|floating-point]] numbers. Progressively, developers refined and remade these early designs into some of the common modern SIMD specifications, which are usually associated with one [[instruction set architecture]] (ISA). Some notable modern examples include Intel's [[Streaming SIMD Extensions]] (SSE) and the PowerPC-related [[AltiVec]] (also known as VMX).{{Efn|Although SSE/SSE2/SSE3 have superseded MMX in Intel's general-purpose processors, later [[IA-32]] designs still support MMX. This is usually done by providing most of the MMX functionality with the same hardware that supports the much more expansive SSE instruction sets.}}

===Hardware performance counter===
{{Main|Hardware performance counter}}
Many modern architectures (including embedded ones) often include [[hardware performance counter]]s (HPC), which enables low-level (instruction-level) collection, [[Benchmark (computing)|benchmarking]], debugging or analysis of running software metrics.<ref>{{Cite conference|last1=Uhsadel|first1=Leif|last2=Georges|first2=Andy|last3=Verbauwhede|first3=Ingrid|date=August 2008|title=Exploiting Hardware Performance Counters|url=https://ieeexplore.ieee.org/document/4599558|conference=2008 5th Workshop on Fault Diagnosis and Tolerance in Cryptography|pages=59–67|doi=10.1109/FDTC.2008.19|isbn=978-0-7695-3314-8|s2cid=1897883|access-date=2021-12-30|archive-date=2021-12-30|archive-url=https://web.archive.org/web/20211230134328/https://ieeexplore.ieee.org/document/4599558/|url-status=live|url-access=subscription}}</ref><ref>{{Cite conference|last=Rohou|first=Erven|date=September 2012|title=Tiptop: Hardware Performance Counters for the Masses|url=https://ieeexplore.ieee.org/document/6337508|conference=2012 41st International Conference on Parallel Processing Workshops|pages=404–413|doi=10.1109/ICPPW.2012.58|isbn=978-1-4673-2509-7|s2cid=16160098|access-date=2021-12-30|archive-date=2021-12-30|archive-url=https://web.archive.org/web/20211230134326/https://ieeexplore.ieee.org/document/6337508/|url-status=live}}</ref> HPC may also be used to discover and analyze unusual or suspicious activity of the software, such as [[return-oriented programming]] (ROP) or [[sigreturn-oriented programming]] (SROP) exploits etc.<ref>{{Cite web|last1=Herath|first1=Nishad|last2=Fogh|first2=Anders|date=2015|title=CPU Hardware Performance Counters for Security|url=https://www.blackhat.com/docs/us-15/materials/us-15-Herath-These-Are-Not-Your-Grand-Daddys-CPU-Performance-Counters-CPU-Hardware-Performance-Counters-For-Security.pdf|url-status=live|publisher=Black Hat|location=USA|archive-url=https://web.archive.org/web/20150905090843/https://www.blackhat.com/docs/us-15/materials/us-15-Herath-These-Are-Not-Your-Grand-Daddys-CPU-Performance-Counters-CPU-Hardware-Performance-Counters-For-Security.pdf |archive-date=2015-09-05 }}</ref> This is usually done by software-security teams to assess and find malicious binary programs.<ref>{{Cite book |last=Jøsang |first=Audun |url=https://books.google.com/books?id=-kFmDwAAQBAJ&dq=usually+done+by+software-security+teams+to+assess+and+find+malicious+binary+programs.&pg=PA96 |title=ECCWS 2018 17th European Conference on Cyber Warfare and Security V2 |date=2018-06-21 |publisher=Academic Conferences and publishing limited |isbn=978-1-911218-86-9 |language=en}}</ref>

Many major vendors (such as [[IBM]], [[Intel]], [[AMD]], and [[Arm Holdings|Arm]]) provide software interfaces (usually written in C/C++) that can be used to collect data from the CPU's [[hardware register|register]]s in order to get metrics.<ref>{{Citation|last=DeRose|first=Luiz A.|title=The Hardware Performance Monitor Toolkit|date=2001|url=http://link.springer.com/10.1007/3-540-44681-8_19|work=Euro-Par 2001 Parallel Processing|series=Lecture Notes in Computer Science|volume=2150|pages=122–132|editor-last=Sakellariou|editor-first=Rizos|place=Berlin, Heidelberg|publisher=Springer Berlin Heidelberg|language=en|doi=10.1007/3-540-44681-8_19|isbn=978-3-540-42495-6|access-date=2021-12-30|editor2-last=Gurd|editor2-first=John|editor3-last=Freeman|editor3-first=Len|editor4-last=Keane|editor4-first=John|archive-date=2023-03-01|archive-url=https://web.archive.org/web/20230301143920/https://link.springer.com/chapter/10.1007/3-540-44681-8_19|url-status=live|url-access=subscription}}</ref> Operating system vendors also provide software like <code>[[Perf (Linux)|perf]]</code> (Linux) to record, [[Benchmark (computing)|benchmark]], or [[Tracing (software)|trace]] CPU events running kernels and applications.

Hardware counters provide a low-overhead method for collecting comprehensive performance metrics related to a CPU's core elements (functional units, caches, main memory, etc.) – a significant advantage over software profilers.<ref>{{Cite web |title=TOWARDS A BENCHMARK FOR PERFORMANCE AND POWER CONSUMPTION EVALUATION OF PARALLEL PROGRAMMING INTERFACES |url=https://dspace.unipampa.edu.br/bitstream/riu/4136/1/Adriano%20Marques%20Garcia%20-%202019.pdf |access-date=2024-03-15 |language=vi}}</ref> Additionally, they generally eliminate the need to modify the underlying source code of a program.<ref>{{Cite book |last1=Chawdhury |first1=Tarun Kumar |url=https://books.google.com/books?id=8f34EAAAQBAJ&dq=benefit+of+using+them+is+that+no+source+code+modifications+are+needed+in+general.&pg=PA117 |title=Mastering Secure Java Applications: Navigating security in cloud and microservices for Java |last2=Banerjee |first2=Joyanta |last3=Gupta |first3=Vipul |last4=Poddar |first4=Debopam |date=2024-03-04 |publisher=BPB Publications |isbn=978-93-5551-884-2 |pages=117 |edition=English |language=en}}</ref> Because hardware designs differ between architectures, the specific types and interpretations of hardware counters will also change.