Editing Classic RISC pipeline (section)

====Solution A. Bypassing====

Bypassing is also known as [[operand forwarding]].

Suppose the CPU is executing the following piece of code:
<syntaxhighlight lang="nasm">
SUB r3,r4 -> r10     ; Writes r3 - r4 to r10
AND r10,r3 -> r11    ; Writes r10 & r3 to r11
</syntaxhighlight>
The instruction fetch and decode stages send the second instruction one cycle after the first.  They flow down the pipeline as shown in this diagram:

[[File:Pipeline Data Hazard.svg|center]]

In a ''naive pipeline'', without hazard consideration, the data hazard progresses as follows:

In cycle 3, the <code>SUB</code> instruction calculates the new value for <code>r10</code>. In the same cycle, the <code>AND</code> operation is decoded, and the value of <code>r10</code> is fetched from the register file. However, the <code>SUB</code> instruction has not yet written its result to <code>r10</code>. Write-back of this normally occurs in cycle 5 (green box). Therefore, the value read from the register file and passed to the ALU (in the Execute stage of the <code>AND</code> operation, red box) is incorrect.

Instead, we must pass the data that was computed by <code>SUB</code> back to the Execute stage (i.e. to the red circle in the diagram) of the <code>AND</code> operation ''before'' it is normally written-back. The solution to this problem is a pair of bypass multiplexers.  These multiplexers sit at the end of the decode stage, and their flopped outputs are the inputs to the ALU.  Each multiplexer selects between:
# A register file read port (i.e. the output of the decode stage, as in the naive pipeline): {{red|red}} arrow
# The current register pipeline of the ALU (to bypass by one stage): {{blue|blue}} arrow
# The current register pipeline of the access stage (which is either a loaded value or a forwarded ALU result, this provides bypassing of two stages): {{purple|purple}} arrow. Note that this requires the data to be passed ''backwards'' in time by one cycle. If this occurs, a [[bubble (computing)|bubble]] must be inserted to stall the <code>AND</code> operation until the data is ready.

Decode stage logic compares the registers written by instructions in the execute and access stages of the pipeline to the registers read by the instruction in the decode stage, and cause the multiplexers to select the most recent data.  These bypass multiplexers make it possible for the pipeline to execute simple instructions with just the latency of the ALU, the multiplexer, and a flip-flop.  Without the multiplexers, the latency of writing and then reading the register file would have to be included in the latency of these instructions.

Note that the data can only be passed ''forward'' in time - the data cannot be bypassed back to an earlier stage if it has not been processed yet. In the case above, the data is passed forward (by the time the <code>AND</code> is ready for the register in the ALU, the <code>SUB</code> has already computed it).

[[File:Data Forwarding (One Stage).svg|center]]