Editing Context switch (section)

== {{Anchor|LATENCY}}Performance ==
Context switching itself has a cost in performance, due to running the [[scheduling (computing)|task scheduler]], TLB flushes, and indirectly due to sharing the [[CPU cache]] between multiple tasks.<ref>{{cite conference |conference=ACM [[Federated Computing Research Conference]], San Diego, 13-14 June 2007 |author1=Chuanpeng Li |author2=Chen Ding |author3=Kai Shen |title=Quantifying The Cost of Context Switch |url=https://www.usenix.org/legacy/events/expcs07/papers/2-li.pdf |archive-url=https://web.archive.org/web/20170813225252/https://www.usenix.org/legacy/events/expcs07/papers/2-li.pdf |archive-date=2017-08-13 |url-status=live }}</ref> Switching between threads of a single process can be faster than between two separate processes because threads share the same [[virtual memory]] maps, so a TLB flush is not necessary.<ref>{{cite news |author=Ulrich Drepper |date=9 October 2014 |title=Memory part 3: Virtual Memory |publisher=[[LWN.net]] |url=https://lwn.net/Articles/253361/ }}</ref>

The time to switch between two separate processes is called the '''process switching latency'''. The time to switch between two threads of the same process is called the '''thread switching latency'''. The time from when a hardware interrupt is generated to when the interrupt is serviced is called the [[interrupt latency]].

Switching between two processes in a [[single address space operating system]] can be faster than switching between two processes in an operating system with private per-process address spaces.<ref>
D.L. Sims.
"Multiple and single address spaces: towards a middle ground".
1993.
{{doi|10.1109/IWOOOS.1993.324906}}
</ref>

=== Hardware vs. software ===
Context switching can be performed primarily by software or hardware. Some processors, like the [[Intel 80386]] and its successors,<ref>{{cite web |url=http://www.linfo.org/context_switch.html |title=Context Switch definition |publisher=Linfo.org |access-date=2013-09-08 |archive-url=https://web.archive.org/web/20100218115342/http://www.linfo.org/context_switch.html |archive-date=2010-02-18 |url-status=dead }}</ref> have hardware support for context switches, by making use of a special data segment designated the [[task state segment]] (TSS). A task switch can be explicitly triggered with a CALL or JMP instruction targeted at a TSS descriptor in the [[global descriptor table]]. It can occur implicitly when an interrupt or exception is triggered if there is a [[task gate]] in the [[interrupt descriptor table]] (IDT). When a task switch occurs, the CPU can automatically load the new state from the TSS.

As with other tasks performed in hardware, one would expect this to be rather fast; however, mainstream operating systems, including [[Microsoft Windows|Windows]] and [[Linux]],<ref>{{cite book|url=https://books.google.com/books?id=h0lltXyJ8aIC&q=Linux+hardware+TSS&pg=PA104|title=Understanding the Linux Kernel, Third Edition|last1=Bovet|first1=Daniel Pierre|last2=Cesati|first2=Marco|publisher=[[O'Reilly Media]]|year=2006|page=104|access-date=2009-11-23|isbn=978-0-596-00565-8}}</ref> do not use this feature. This is mainly due to two reasons:

* Hardware context switching does not save all the registers (only general-purpose registers, not [[floating point|floating-point]] registers — although the <code>TS</code> bit is automatically turned on in the <code>CR0</code> [[control register]], resulting in a fault when executing floating-point [[Instruction (computer science)|instructions]] and giving the OS the opportunity to save and restore the floating-point state as needed).
* Associated performance issues, e.g., software context switching can be selective and store only those registers that need storing, whereas hardware context switching stores nearly all registers whether they are required or not.