Editing Dynamic random-access memory (section)

==Memory cell design==
{{See also|Memory cell (computing)}}
Each bit of data in a DRAM is stored as a positive or negative electrical charge in a capacitive structure. The structure providing the capacitance, as well as the transistors that control access to it, is collectively referred to as a ''DRAM cell''. They are the fundamental building block in DRAM arrays. Multiple DRAM memory cell variants exist, but the most commonly used variant in modern DRAMs is the one-transistor, one-capacitor (1T1C) cell. The transistor is used to admit current into the capacitor during writes, and to discharge the capacitor during reads. The access transistor is designed to maximize drive strength and minimize transistor-transistor leakage (Kenner, p.&nbsp;34). <!--The design of the memory cell varies by DRAM manufacturer and process.-->

The capacitor has two terminals, one of which is connected to its access transistor, and the other to either ground or V<sub>CC</sub>/2. In modern DRAMs, the latter case is more common, since it allows faster operation. In modern DRAMs, a voltage of +V<sub>CC</sub>/2 across the capacitor is required to store a logic one; and a voltage of &minus;V<sub>CC</sub>/2 across the capacitor is required to store a logic zero. The resultant charge is <math display ="inline">Q = \pm {V_{CC} \over 2} \cdot C</math>, where ''Q'' is the charge in [[coulomb]]s and ''C'' is the capacitance in [[farad]]s.<ref name="Kenner:22">{{harvnb|Keeth|Baker|Johnson|Lin|2007|p=22}}</ref>

Reading or writing a logic one requires the wordline be driven to a voltage greater than the sum of V<sub>CC</sub> and the access transistor's threshold voltage (V<sub>TH</sub>). This voltage is called ''V<sub>CC</sub> pumped'' (V<sub>CCP</sub>). The time required to discharge a capacitor thus depends on what logic value is stored in the capacitor. A capacitor containing logic one begins to discharge when the voltage at the access transistor's gate terminal is above V<sub>CCP</sub>. If the capacitor contains a logic zero, it begins to discharge when the gate terminal voltage is above V<sub>TH</sub>.<ref name="Kenner:24">{{harvnb|Keeth|Baker|Johnson|Lin|2007|p=24}}</ref>

===Capacitor design===
Up until the mid-1980s, the capacitors in DRAM cells were co-planar with the access transistor (they were constructed on the surface of the substrate), thus they were referred to as ''planar'' capacitors. The drive to increase both density and, to a lesser extent, performance, required denser designs. This was strongly motivated by economics, a major consideration for DRAM devices, especially commodity DRAMs. The minimization of DRAM cell area can produce a denser device and lower the cost per bit of storage. Starting in the mid-1980s, the capacitor was moved above or below the silicon substrate in order to meet these objectives. DRAM cells featuring capacitors above the substrate are referred to as ''stacked'' or ''folded plate'' capacitors. Those with capacitors buried beneath the substrate surface are referred to as ''trench'' capacitors. In the 2000s, manufacturers were sharply divided by the type of capacitor used in their DRAMs and the relative cost and long-term scalability of both designs have been the subject of extensive debate. The majority of DRAMs, from major manufactures such as [[Hynix]], [[Micron Technology]], [[Samsung Electronics]] use the stacked capacitor structure,<!--where a cylindrical and tall capacitor is stacked on top of the transistor--> whereas smaller manufacturers such Nanya Technology use the trench capacitor structure (Jacob, pp.&nbsp;355–357).

The capacitor in the stacked capacitor scheme is constructed above the surface of the substrate. The capacitor is constructed from an oxide-nitride-oxide (ONO) dielectric sandwiched in between two layers of polysilicon plates (the top plate is shared by all DRAM cells in an IC), and its shape can be a rectangle, a cylinder, or some other more complex shape. There are two basic variations of the stacked capacitor, based on its location relative to the bitline&mdash;capacitor-under-bitline (CUB) and capacitor-over-bitline (COB). In the former, the capacitor is underneath the bitline, which is usually made of metal, and the bitline has a polysilicon contact that extends downwards to connect it to the access transistor's source terminal. In the latter, the capacitor is constructed above the bitline, which is almost always made of polysilicon, but is otherwise identical to the COB variation. The advantage the COB variant possesses is the ease of fabricating the contact between the bitline and the access transistor's source as it is physically close to the substrate surface. However, this requires the active area to be laid out at a 45-degree angle when viewed from above, which makes it difficult to ensure that the capacitor contact does not touch the bitline. CUB cells avoid this, but suffer from difficulties in inserting contacts in between bitlines, since the size of features this close to the surface are at or near the minimum feature size of the process technology (Kenner, pp.&nbsp;33–42).

The trench capacitor is constructed by etching a deep hole into the silicon substrate. The substrate volume surrounding the hole is then heavily doped to produce a buried n<sup>+</sup> plate with low resistance. A layer of oxide-nitride-oxide dielectric is grown or deposited, and finally the hole is filled by depositing doped polysilicon, which forms the top plate of the capacitor. The top of the capacitor is connected to the access transistor's drain terminal via a polysilicon strap (Kenner, pp.&nbsp;42–44). A trench capacitor's depth-to-width ratio in DRAMs of the mid-2000s can exceed 50:1 (Jacob, p.&nbsp;357).

Trench capacitors have numerous advantages. Since the capacitor is buried in the bulk of the substrate instead of lying on its surface, the area it occupies can be minimized to what is required to connect it to the access transistor's drain terminal without decreasing the capacitor's size, and thus capacitance (Jacob, pp.&nbsp;356–357). Alternatively, the capacitance can be increased by etching a deeper hole without any increase to surface area (Kenner, p.&nbsp;44). Another advantage of the trench capacitor is that its structure is under the layers of metal interconnect, allowing them to be more easily made planar, which enables it to be integrated in a logic-optimized process technology, which have many levels of interconnect above the substrate. The fact that the capacitor is under the logic means that it is constructed before the transistors are. This allows high-temperature processes to fabricate the capacitors, which would otherwise degrade the logic transistors and their performance. This makes trench capacitors suitable for constructing [[embedded DRAM]] (eDRAM) (Jacob, p.&nbsp;357). Disadvantages of trench capacitors are difficulties in reliably constructing the capacitor's structures within deep holes and in connecting the capacitor to the access transistor's drain terminal (Kenner, p.&nbsp;44).

===Historical cell designs===
First-generation DRAM ICs (those with capacities of 1&nbsp;Kbit), such as the archetypical [[Intel 1103]], used a three-transistor, one-capacitor (3T1C) DRAM cell with separate read and write circuitry.  The write wordline drove a write transistor which connected the capacitor to the write bitline just as in the 1T1C cell, but there was a separate read wordline and read transistor which connected an amplifier transistor to the read bitline.  By the second generation, the drive to reduce cost by fitting the same amount of bits in a smaller area led to the almost universal adoption of the 1T1C DRAM cell, although a couple of devices with 4 and 16&nbsp;Kbit capacities continued to use the 3T1C cell for performance reasons (Kenner, p.&nbsp;6). These performance advantages included, most significantly, the ability to read the state stored by the capacitor without discharging it, avoiding the need to write back what was read out (non-destructive read). A second performance advantage relates to the 3T1C cell's separate transistors for reading and writing; the memory controller can exploit this feature to perform atomic read-modify-writes, where a value is read, modified, and then written back as a single, indivisible operation (Jacob, p.&nbsp;459).

===Proposed cell designs===
The one-transistor, zero-capacitor (1T, or 1T0C) DRAM cell has been a topic of research since the late-1990s. ''1T DRAM'' is a different way of constructing the basic DRAM memory cell, distinct from the classic one-transistor/one-capacitor (1T/1C) DRAM cell, which is also sometimes referred to as ''1T DRAM'', particularly in comparison to the 3T and 4T DRAM which it replaced in the 1970s.

In 1T DRAM cells, the bit of data is still stored in a capacitive region controlled by a transistor, but this capacitance is no longer provided by a separate capacitor. 1T DRAM is a "capacitorless" bit cell design that stores data using the parasitic body capacitance that is inherent to [[silicon on insulator]] (SOI) transistors. Considered a nuisance in logic design, this [[floating body effect]] can be used for data storage. This gives 1T DRAM cells the greatest density as well as allowing easier integration with high-performance logic circuits since they are constructed with the same SOI process technologies.<ref>{{cite web |url=https://aes2.org/publications/par/num/ |title=Pro Audio Reference |access-date=2024-08-08}}</ref>

Refreshing of cells remains necessary, but unlike with 1T1C DRAM, reads in 1T DRAM are non-destructive; the stored charge causes a detectable shift in the [[threshold voltage]] of the transistor.<ref>{{cite conference|first=Jean-Michel|last=Sallese|title=Principles of the 1T Dynamic Access Memory Concept on SOI|conference=MOS Modeling and Parameter Extraction Group Meeting|location=Wroclaw, Poland|date=2002-06-20|url=http://legwww.epfl.ch/ekv/mos-ak/wroclaw/MOS-AK_JMS.pdf|access-date=2007-10-07|url-status=dead|archive-url=https://web.archive.org/web/20071129114317/http://legwww.epfl.ch/ekv/mos-ak/wroclaw/MOS-AK_JMS.pdf|archive-date=2007-11-29}}</ref> Performance-wise, access times are significantly better than capacitor-based DRAMs, but slightly worse than SRAM. There are several types of 1T DRAMs: the commercialized [[Z-RAM]] from Innovative Silicon, the TTRAM<ref>{{cite book|author1=F. Morishita|title=Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005|display-authors=etal|chapter=A capacitorless twin-transistor random access memory (TTRAM) on SOI|date=21 September 2005|volume=Custom Integrated Circuits Conference 2005|pages=428–431|doi=10.1109/CICC.2005.1568699|isbn=978-0-7803-9023-2|s2cid=14952912}}</ref> from Renesas and the [[A-RAM]] from the [[University of Granada|UGR]]/[[CNRS]] consortium.