Editing Electromigration (section)

== Electromigration-aware design ==

=== Electromigration reliability of a wire (Black's equation) ===
{{main | Black's equation }}

At the end of the 1960s J. R. Black developed an empirical model to estimate the [[MTTF]] (mean time to failure) of a wire, taking electromigration into consideration. Since then, the formula has gained popularity in the semiconductor industry:<ref name="Black" /><ref>{{cite book |title=Handbook of multilevel metallization for integrated circuits: materials, technology, and applications |first1=Syd R. |last1=Wilson |first2=Clarence J. |last2=Tracy |first3=John L. |last3=Freeman |publisher=William Andrew |year=1993 |isbn=978-0-8155-1340-7 |page=607 |url=https://books.google.com/books?id=jHeN7KYkj28C}}, [https://books.google.com/books?id=jHeN7KYkj28C&pg=PA607 Page 607, equation 24]</ref>

:<math>\text{MTTF} = \frac{A}{J^n} \exp{\left(\frac{E_\text{a}}{k T}\right)}</math>.

Here <math>A</math> is a constant based on the cross-sectional area of the interconnect, <math>J</math> is the current density, <math>E_\text{a}</math> is the [[activation energy]] (e.g. 0.7 eV for grain boundary diffusion in aluminum), <math>k</math> is the [[Boltzmann constant]], <math>T</math> is the temperature in [[kelvin]]s, and <math>n</math> a scaling factor (usually set to 2 according to Black).<ref name="Black" /> The temperature of the conductor appears in the exponent, i.e. it strongly affects the MTTF of the interconnect. For an interconnect of a given construction to remain reliable as the temperature rises, the current density within the conductor must be reduced. However, as interconnect technology advances at the nanometer scale, the validity of Black's equation becomes increasingly questionable.

=== Wire material ===
Historically, aluminium has been used as conductor in integrated circuits, due to its good adherence to substrate, good conductivity, and ability to form [[ohmic contact]]s with silicon.<ref name="EM_book" /> However, pure aluminium is susceptible to electromigration. Research shows that adding 2-4% of copper to aluminium increases resistance to electromigration about 50 times. The effect is attributed to the grain boundary segregation of copper, which greatly inhibits the diffusion of aluminium atoms across grain boundaries.<ref name="contact_book">{{Cite book|author=M. Braunovic, N. K. Myshkin, V. V. Konchits|title=Electrical Contacts: Fundamentals, Applications and Technology|url=https://www.crcpress.com/Electrical-Contacts-Fundamentals-Applications-and-Technology/Braunovic-Myshkin-Konchits/p/book/9781574447279|publisher=CRC Press|date=2006|isbn=978-1-5744-47279}}</ref>

Pure copper wires can withstand approximately five times more current density than aluminum wires while maintaining similar reliability requirements.<ref name="Lienig" >J. Lienig: "Introduction to Electromigration-Aware Physical Design" [http://www.ifte.de/mitarbeiter/lienig/ispd06_emPaper_lienig.pdf (Download paper)], ''Proc. of the Int. Symposium on Physical Design (ISPD) 2006'', pp. 39–46, April 2006.</ref> This is mainly due to the higher electromigration activation energy levels of copper, caused by its superior electrical and thermal conductivity as well as its higher melting point. Further improvements can be achieved by alloying copper with about 1% [[palladium]] which inhibits diffusion of copper atoms along grain boundaries in the same way as the addition of copper to aluminium interconnect.

=== Bamboo structure and metal slotting ===
A wider wire results in smaller current density and, hence, less likelihood of electromigration. Also, the metal grain size has influence; the smaller grains, the more grain boundaries and the higher likelihood of electromigration effects. However, if you reduce wire width to below the average grain size of the wire material, grain boundaries become "crosswise", more or less perpendicular to the length of the wire. The resulting structure resembles the joints in a stalk of bamboo. With such a structure, the resistance to electromigration increases, despite an increase in current density. This apparent contradiction is caused by the perpendicular position of the grain boundaries; the boundary diffusion factor is excluded, and material transport is correspondingly reduced.<ref name="Lienig" /><ref name="Zamri">M. Zamri ''et al'' "In Situ TEM Observation of Fe-Included Carbon Nanofiber: Evolution of Structural and Electrical Properties in Field Emission Process", ACS Nano, 2012, 6 (11), pp 9567–9573. [Link http://pubs.acs.org/doi/abs/10.1021/nn302889e]</ref>

However, the maximum wire width possible for a bamboo structure is usually too narrow for signal lines of large-magnitude currents in analog circuits or for power supply lines. In these circumstances, slotted wires are often used, whereby rectangular holes are carved in the wires. Here, the widths of the individual metal structures in between the slots lie within the area of a bamboo structure, while the resulting total width of all the metal structures meets power requirements.<ref name="Lienig" /><ref name="Zamri"/>

=== Blech length ===
There is a lower limit for the length of the interconnect that will allow higher current carrying capability. It is known as "Blech length".<ref name="Blech" /> Any wire that has a length below this limit will have a stretched limit for electromigration. Here, a mechanical stress buildup causes an atom back flow process which reduces or even compensates the effective material flow towards the anode. The Blech length must be considered when designing test structures to evaluate electromigration. This minimum length is typically some tens of microns for chip traces, and interconnections shorter than this are sometimes referred to as 'electromigration immortal'.

=== Via arrangements and corner bends ===
Particular attention must be paid to [[Via (electronics)|vias]] and contact holes. The current carrying capacity of a via is much less than a metallic wire of same length. Hence multiple vias are often used, whereby the geometry of the via array is very significant: multiple vias must be organized such that the resulting current is distributed as evenly as possible through all the vias.

Attention must also be paid to bends in interconnects. In particular, 90-degree corner bends must be avoided, since the current density in such bends is significantly higher than that in oblique angles (e.g., 135 degrees).<ref name="Lienig" />

=== Electromigration in solder joints ===
The typical current density at which electromigration occurs in Cu or Al interconnects is 10<sup>6</sup> to 10<sup>7</sup> A/cm<sup>2</sup>. For solder joints (SnPb or SnAgCu lead-free) used in IC chips, however, electromigration occurs at much lower current densities, e.g. 10<sup>4</sup> A/cm<sup>2</sup>.
It causes a net atom transport along the direction of electron flow. The atoms accumulate at the anode, while voids are generated at the cathode and back stress is induced during electromigration. The typical failure of a solder joint due to electromigration will occur at the cathode side. Due to the current crowding effect, voids form first at the corners of the solder joint. Then the voids extend and join to cause a failure. Electromigration also influences formation of [[intermetallic compound]]s, as the migration rates are a function of atomic mass.

=== Electromigration and technology computer aided design ===
The complete mathematical model describing electromigration consists of several partial differential equations (PDEs) <ref name="Basaran_Lin03" >C. Basaran, M. Lin, and H. Ye : ''A Thermodynamic Model for Electrical Current Induced Damage.'' International Journal of Solids and Structures, Vol 40, pp. 7315-7327, 2003.</ref> which need to be solved for three-dimensional geometrical domains representing segments of an interconnect structure. Such a mathematical model forms the basis for simulation of electromigration in modern technology computer aided design (TCAD) tools.<ref name="Ceric_Selberherr11" >{{cite journal|last1=Ceric|first1=H.|last2=Selberherr|first2=S.|title=Electromigration in submicron interconnect features of integrated circuits|journal=Materials Science and Engineering: R: Reports|volume=71|issue=5–6|year=2011|pages=53–86|issn=0927-796X|doi=10.1016/j.mser.2010.09.001}}</ref>
Use of TCAD tools for detailed investigations of electromigration induced interconnect degradation is gaining importance. Results of TCAD studies in combination with reliability tests lead to modification of design rules improving the interconnect resistance to electromigration.<ref name="Orio_Ceric12" >{{cite journal|last1=de Orio|first1=R.L.|last2=Ceric|first2=H.|last3=Selberherr|first3=S.|title=Electromigration failure in a copper dual-damascene structure with a through silicon via|journal=Microelectronics Reliability|volume=52|issue=9–10|year=2012|pages=1981–1986|issn=0026-2714|doi=10.1016/j.microrel.2012.07.021|pmid=23564974|pmc=3608028|bibcode=2012MiRe...52.1981D }}</ref>

=== Electromigration due to IR drop noise of the on-chip power grid network/interconnect ===
{{Confusing section|date=February 2022}}
The electromigration degradation of the on-chip power grid network/interconnect depends on the IR drop noise of the power grid interconnect.
The electromigration-aware lifetime of the power grid interconnects as well as the chip decreases if the chip suffers from a high value of the IR drop noise.<ref>{{Cite book |doi = 10.1109/ISVLSI.2018.00018|chapter = PGIREM: Reliability-Constrained IR Drop Minimization and Electromigration Assessment of VLSI Power Grid Networks Using Cooperative Coevolution|title = 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)|pages = 40–45|year = 2018|last1 = Dey|first1 = Sukanta|last2 = Dash|first2 = Satyabrata|last3 = Nandi|first3 = Sukumar|last4 = Trivedi|first4 = Gaurav|isbn = 978-1-5386-7099-6|s2cid = 51984331}}</ref>

=== Machine Learning Model for Electromigration-aware MTTF Prediction===
{{Confusing section|date=February 2022}}
Recent work demonstrates MTTF prediction using a machine learning model. The work uses a neural network-based supervised learning approach with current density, interconnect length, interconnect temperature as input features to the model.<ref>{{Cite journal |doi = 10.1145/3399677 |pages = 1–29|year = 2020|last1 = Dey|first1 = Sukanta|last2 = Nandi|first2 = Sukumar|last3 = Trivedi|first3 = Gaurav | title=Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-chip Power Grid Network | journal=ACM Transactions on Design Automation of Electronic Systems |volume = 25|issue = 5|s2cid = 222110488}}</ref><ref>{{Cite journal|url=https://dl.acm.org/doi/10.1145/3399677?cid=99659544720|doi=10.1145/3399677 |year=2020|last1=Dey|first1=Sukanta|last2=Nandi|first2=Sukumar|last3=Trivedi|first3=Gaurav |title=Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-chip Power Grid Network |journal=ACM Transactions on Design Automation of Electronic Systems |volume=25|issue=5|pages=1–29|s2cid=222110488|url-access=subscription}}</ref>