Editing Hardware description language (section)

== Examples of HDLs ==
=== HDLs for analog circuit design ===

{| class="sortable wikitable"
|-
! Name
! Description
|-
| [[HDL-A]]
| A proprietary analog HDL
|-
| SpectreHDL
| A proprietary analog HDL from [[Cadence Design Systems]] for its Spectre circuit simulator
|-
| [[Verilog-AMS]] (Verilog for Analog and Mixed-Signal)
| An [[Accellera]] standard extension of IEEE&nbsp;Std&nbsp;1364 [[Verilog]] for analog and mixed-signal simulation
|-
| [[VHDL-AMS]] (VHDL with Analog/Mixed-Signal extension)
| An [[IEEE Standards Association|IEEE standard]] extension (IEEE&nbsp;Std&nbsp;1076.1) of [[VHDL]] for analog and mixed-signal simulation
|}

=== HDLs for digital circuit design ===

The two most widely used and well-supported HDL varieties used in industry are [[Verilog]] and [[VHDL]].

{| class="sortable wikitable"
|-
! Status
! Name
! Host [[Programming language|language]]
! Description
|-
! rowspan="47" |In use
| [[Altera Hardware Description Language]] (AHDL)
|
| [[Proprietary software|Proprietary]] language from [[Altera]]
|-
| A Hardware Programming language ([[AHPL]])
|
| Used as a tool for teaching
|-
| [https://github.com/amaranth-lang/amaranth Amaranth]
| [[Python (programming language)|Python]]
|
|-
| [[Bluespec]]
|
| High-level HDL based on [[Haskell]] (not embedded [[Domain-specific language|DSL]])<ref>''A History of Haskell: being lazy with class'' §12.4.2</ref>
|-
| [[Bluespec]] [[SystemVerilog]] (BSV)
|
| Based on [[Bluespec]], with [[Verilog]] HDL like syntax, by Bluespec, Inc.
|-
| C-to-Verilog
|
| Converter from C to Verilog
|-
| [[Chisel (programming language)|Chisel]] (Constructing Hardware in a Scala Embedded Language)<ref>{{Cite web |url=https://www.chisel-lang.org/ |title=Chisel/FIRRTL Hardware Compiler Framework}}</ref>
| [[Scala (programming language)|Scala]]
| Based on [[Scala (programming language)|Scala]] (embedded [[Domain-specific language|DSL]])
|-
| [https://clash-lang.org/ Clash] 
|
| Functional hardware description language that borrows its syntax and semantics from the functional language [[Haskell]]
|-
| Common Oriented Language for Architecture of Multi Objects (COLAMO)<ref>[https://web.archive.org/web/20091109155107/http://colamo.parallel.ru/ COLAMO]</ref><ref>{{Cite web |url=http://superevm.ru/index.php?page=higher-level-language-colamo |title=Higher-level language COLAMO – НИЦ супер-ЭВМ и нейрокомпьютеров}}</ref>
|
| [[Proprietary software|Proprietary]] language from “Supercomputers and Neurocomputers Research Center” Co Ltd.
|-
| Compiler for Universal Programmable Logic (CUPL)<ref>{{Cite journal |last1=Eurich |first1=J.P. |last2=Roth |first2=G. |year=1990 |title=EDIF grows up |journal=IEEE Spectrum |volume=27 |issue=11 |pages=68–72 |doi=10.1109/6.62219 |s2cid=381119}}</ref>
|
| [[Proprietary software|Proprietary]] language from Logical Devices, Inc.
|-
| [https://google.github.io/xls/dslx_reference DSLX]
|
| [[Domain-specific language]] for XLS toolchain
|-
| ESys.net
|
| [[.NET]] framework written in C#
|-
|[https://filamenthdl.com/ Filament]
|
|HDL with a type system inspired by Rust
|-
| [[Handel-C]]
|
| C-like design language
|-
| [https://github.com/ujamjar/hardcaml Hardcaml]
| [[OCaml]]
| Based on [[OCaml]] (embedded DSL)<ref>[http://www.ujamjar.com/hardcaml/ Hardcaml]</ref>
|-
| HHDL
| [[Haskell]]
| Based on [[Haskell]] (embedded DSL)
|-
| Hardware [[Join-pattern|Join Java]] (HJJ)
| [[Join-pattern|Join Java]]
| Based on [[Join-pattern|Join Java]]
|-
| Hardware ML (HML)
| [[Standard ML]]
| Based on [[Standard ML]]<ref>{{Cite book |last1=Li |first1=Yanbing |last2=Leeser |first2=M. |year=1995 |chapter=HML: An innovative hardware description language and its translation to VHDL |title=Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair |pages=691–696 |doi=10.1109/ASPDAC.1995.486388 |isbn=4-930813-67-0 |s2cid=14198160}}</ref>
|-
| Hydra
| [[Haskell]]
| Based on [[Haskell]]
|-
| [[Impulse C]]
|
| C-like HDL
|-
| Parallel C++ (ParC)
|
| kusu extended with HDL style threading and communication for task-parallel programming
|-
| JHDL
| [[Java (programming language)|Java]]
| Based on [[Java (programming language)|Java]]
|-
| Lava
| [[Haskell]]
| Based on [[Haskell]] (embedded DSL)<ref>[http://hackage.haskell.org/package/chalmers-lava2000 Chalmers Lava]</ref><ref>[http://hackage.haskell.org/package/xilinx-lava Xilinx Lava]</ref><ref>[http://hackage.haskell.org/package/kansas-lava Kansas Lava]</ref><ref>[http://hackage.haskell.org/package/york-lava York Lava]</ref>
|-
| [[Lola (hardware description language)|Lola]]
|
| Simple language used for teaching
|-
| [[M (HDL)|M]]
|
| HDL from [[Mentor Graphics]]
|-
| [https://github.com/m-labs/migen Migen]
| [[Python (programming language)|Python]]
|
|-
| [[MyHDL]]
| [[Python (programming language)|Python]]
| Based on [[Python (programming language)|Python]] (embedded [[Domain-specific language|DSL]])
|-
| [[PALASM]]
|
| For [[Programmable Array Logic]] (PAL) devices
|-
| [https://github.com/JulianKemmerer/PipelineC PipelineC]
|
| C-like hardware description language adding [[High-level synthesis]]-like automatic pipelining as a language construct and compiler feature.
|-
| [https://github.com/pymtl/pymtl3 PyMTL 3 (Mamba)]
| [[Python (programming language)|Python]]
| Based on Python, from Cornell University
|-
| [https://ucsbarchlab.github.io/PyRTL/ PyRTL]
| [[Python (programming language)|Python]]
| Based on Python, from University of California, Santa Barbara
|-
| Riverside Optimizing Compiler for Configurable Computing (ROCCC)
|
| Free and open-source C to HDL tool
|-
| RHDL
| [[Ruby (programming language)|Ruby]]
| Based on the [[Ruby (programming language)|Ruby programming language]]
|-
| Rapid Open Hardware Development (ROHD)<ref>{{Cite web |url=https://github.com/intel/rohd |title=Rapid Open Hardware Development (ROHD) Framework
| website=[[GitHub]]
| date=17 November 2021
}}</ref>
| [[Dart (programming language)|Dart]]
| [[Software framework|Framework]] for hardware design and verification, written in [[Dart (programming language)|Dart]]
|-
| [[Ruby (hardware description language)]]
|
|
|-
| [https://github.com/sylefeb/Silice Silice]
|
| HDL that simplifies designing hardware algorithms with parallelism and pipelines
|-
| [https://spade-lang.org/ Spade]
|
| HDL inspired by modern software languages like Rust
|-
| [[SystemC]]
|
| Standardized class of [[C++]] libraries for high-level behavioral and transaction modeling of [[digital hardware]] at a high level of abstraction, i.e., system-level
|-
| [[SystemVerilog]]
|
| Superset of Verilog, with enhancements to address system-level design and verification
|-
| [https://github.com/SpinalHDL/SpinalHDL SpinalHDL]
| [[Scala (programming language)|Scala]]
| Based on Scala (embedded DSL)
|-
| SystemTCL
|
| SDL based on Tcl
|-
| Templated HDL inspired by C++ (THDL++)
|
| Extension of VHDL with inheritance, advanced templates and policy classes
|-
| [https://github.com/frwang96/verik Verik]
|
| [[Kotlin (programming language)|Kotlin]] reinterpreted with the semantics of an HDL; transpiled to [[SystemVerilog]]
|-
| Transaction-Level Verilog (TL-Verilog)<ref>[http://www.tl-x.org TL-Verilog]</ref>
|
| Extension of Verilog/[[SystemVerilog]] with constructs for [[Pipeline (computing)|pipelines]] and [[Transactional memory|transactions]].
|-
| [[Verilog]]
|
| One of the most widely used and well-supported HDLs
|-
| [https://veryl-lang.org/ Veryl]
|
| HDL designed as SystemVerilog alternative
|-
| [[VHDL]] ([[VHSIC]] HDL)
|
| One of the most widely used and well-supported HDLs
|-
! rowspan="7" |No longer in common use
| [[Advanced Boolean Expression Language]] (ABEL)
|
| Obsolete HDL made by [[Data I/O Corporation]] in 1983
|-
| Confluence
|
| Functional HDL, discontinued
|-
| CoWareC
|
| C-based HDL by [[CoWare]]; discontinued in favor of SystemC
|-
| [[ELLA (programming language)|ELLA]]
|
| No longer in common use
|-
| ISPS
|
| Original HDL from CMU; no longer in common use
|-
| KAiserslautern Register Language (KARL)<ref name="Hartenstein93"/>
|
| [[Pascal (programming language)|Pascal]]-like hardware description language; no longer in common use
|-
| [https://gitlab.com/nmigen/nmigen nMigen]
| [[Python (programming language)|Python]]
| Predecessor to Amaranth
|}

=== HDLs for printed circuit board design ===

Several projects exist for defining [[printed circuit board]] connectivity using language based, textual-entry methods. Among these, new approaches have emerged that focus on enhancing readability, reusability, and validation. These modern methodologies employ open-source design languages specifically tailored for electronics, adopting declarative markup to specify what circuits should achieve. This shift integrates software development principles into hardware design, streamlining the process and emphasizing automation, reuse, and validation.

{| class="sortable wikitable"
|-
! Name
! Description
|-
| [https://github.com/atopile/atopile atopile]
| An open-source language and toolchain to describe electronic circuit boards with code.
|-
| [[PHDL]] (PCB HDL)
| A free and open source HDL for defining printed circuit board connectivity.
|-
| EDAsolver
| An HDL for solving schematic designs based on constraints.
|-
| [https://github.com/xesscorp/skidl SKiDL]
| Open source Python module to design electronic circuits.
|}