Editing IBM System/360 (section)

===Architectural overview===
{{Main|IBM System/360 architecture}}

The System/360 series [[computer architecture]] specification makes no assumptions on the implementation itself, but rather describes the interfaces and expected behavior of an implementation.<ref name=A22-6821/><ref name=A22-6821-8/><ref name=A22-6843/> The architecture describes mandatory interfaces that must be available on all implementations, and optional interfaces. Some aspects of this architecture are:
* [[Big endian]] byte ordering
* A processor with:
** 16 [[32-bit computing|32-bit]] [[general-purpose register]]s (R0–R15)
** A 64-bit [[program status word]] (PSW), which describes (among other things)
*** [[Interrupt]] masks
*** Privilege states
*** A condition code
*** A 24-bit [[program counter|instruction address]]
** An interruption mechanism, [[interrupt|maskable]] and unmaskable interruption classes and subclasses
** An [[instruction set]]. Each instruction is wholly described and also defines the conditions under which an exception is recognized in the form of program interruption.
* A [[primary storage|memory (called storage) subsystem]] with:
** 8 bits per byte
** A special processor communication area starting at address 0
** 24-bit addressing
* Manual control operations that allow
** A [[booting|bootstrap]] process (a process called Initial Program Load or IPL)
** Operator-initiated interrupts
** Resetting the system
** Basic debugging facilities
** Manual display and modifications of the system's state (memory and processor)
* An Input/Output mechanism{{snd}} which does not describe the devices themselves

Some of the optional features are:
* [[Binary-coded decimal]] instructions
* [[Floating-point arithmetic|Floating-point]] instructions
* Timing facilities (interval timer)
* [[Memory protection key|Key-controlled memory protection]]

All models of System/360, except for the Model 20 and Model 44, implemented that specification.

Binary arithmetic and logical operations are performed as register-to-register and as memory-to-register/register-to-memory as a standard feature. If the Commercial Instruction Set option was installed, [[Binary-coded decimal|packed decimal]] arithmetic could be performed as memory-to-memory with some memory-to-register operations. The Scientific Instruction Set feature, if installed, provided access to four [[floating-point arithmetic|floating-point]] registers that could be programmed for either [[32-bit computing|32-bit]] or [[64-bit computing|64-bit]] floating-point operations. The Models 85 and 195 could also operate on 128-bit extended-precision floating-point numbers stored in pairs of floating-point registers, and software provided emulation in other models. The System/360 used an 8-bit byte, 32-bit word, 64-bit double-word, and 4-bit [[nybble|nibble]]. Machine instructions had operators with operands, which could contain register numbers or memory addresses. This complex combination of instruction options resulted in a variety of instruction lengths and formats.

Memory addressing was accomplished using a base-plus-displacement scheme, with registers 1 through F (15). A displacement was encoded in 12 bits, thus allowing a 4096-byte displacement (0–4095), as the offset from the address put in a base register.

Register 0 could not be used as a base register nor as an index register (nor as a branch address register), as "0" was reserved to indicate an address in the first 4&nbsp;KB of memory, that is, if register 0 was specified as described, the value 0x00000000 was implicitly input to the effective address calculation in place of whatever value might be contained within register 0 (or if specified as a branch address register, then no branch was taken, and the content of register 0 was ignored, but any side effect of the instruction was performed).

This specific behavior permitted initial execution of an interrupt routines, since base registers would not necessarily be set to 0 during the first few instruction cycles of an interrupt routine. It isn't needed for [[Initial Program Load|IPL]] ("Initial Program Load" or boot), as one can always clear a register without the need to save it.

With the exception of the Model 67,<ref name=GA27-2719/> all addresses were real memory addresses. Virtual memory was not available in most IBM mainframes until the [[System/370]] series. The Model 67 introduced a virtual memory architecture, which [[Michigan Terminal System|MTS]], [[CP-67]], and [[TSS/360]] used—but not IBM's mainline System/360 operating systems.

The System/360 machine-code instructions are 2 bytes long (no memory operands), 4 bytes long (one operand), or 6 bytes long (two operands). Instructions are always situated on 2-byte boundaries.

Operations like MVC (Move-Characters) (Hex: D2) can only move at most 256 bytes of information. Moving more than 256 bytes of data required multiple MVC operations. (The [[System/370]] series introduced a family of more powerful instructions such as the MVCL "Move-Characters-Long" instruction, which supports moving up to 16&nbsp;MB as a single block.)

An operand is two bytes long, typically representing an address as a 4-bit [[nybble|nibble]] denoting a base register and a 12-bit displacement relative to the contents of that register, in the range {{mono|000–FFF}} (shown here as [[hexadecimal]] numbers). The address corresponding to that operand is the contents of the specified general-purpose register plus the displacement. For example, an MVC instruction that moves 256 bytes (with length code 255 in hexadecimal as {{mono|FF}}) from base register 7, plus displacement {{mono|000}}, to base register 8, plus displacement {{mono|001}}, would be coded as the 6-byte instruction "{{mono|D2FF 8001 7000}}" (operator/length/address1/address2).

The System/360 was designed to separate the ''system state'' from the ''problem state''. This provided a basic level of security and recoverability from programming errors. Problem (user) programs could not modify data or program storage associated with the system state. Addressing, data, or operation exception errors made the machine enter the system state through a controlled routine so the operating system could try to correct or terminate the program in error. Similarly, it could recover certain processor hardware errors through the ''machine check'' routines.