Editing IBM hexadecimal floating-point (section)

== IEEE 754 on IBM mainframes ==
Starting with the [[S/390]] G5 in 1998,<ref>{{Cite journal |last1=Schwarz |first1=E. M. |last2=Krygowski |first2=C. A. |doi=10.1147/rd.435.0707 |title=The S/390 G5 floating-point unit |journal=[[IBM Journal of Research and Development]] |volume=43 |issue=5.6 |pages=707–721 |date=September 1999}}</ref> IBM mainframes have also included IEEE binary floating-point units which conform to the [[IEEE 754|IEEE 754 Standard for Floating-Point Arithmetic]]. IEEE decimal floating-point was added to [[IBM System z9]] GA2<ref>{{Cite journal |last1=Duale |first1=A. Y. |last2=Decker |first2=M. H. |last3=Zipperer |first3=H.-G. |last4=Aharoni |first4=M. |last5=Bohizic |first5=T. J. |title=Decimal floating-point in z9: An implementation and testing perspective |doi=10.1147/rd.511.0217 |journal=[[IBM Journal of Research and Development]] |volume=51 |issue=1.2 |pages=217–227 |date=January 2007 |citeseerx=10.1.1.123.9055}}</ref> in 2007 using [[millicode]]<ref>{{Cite journal |last1=Heller |first1=L. C. |last2=Farrell |first2=M. S. |doi=10.1147/rd.483.0425 |title=Millicode in an IBM zSeries processor |journal=[[IBM Journal of Research and Development]] |volume=48 |issue=3.4 |pages=425–434 |date=May 2004 |citeseerx=10.1.1.641.1164}}</ref> and in 2008 to the [[IBM System z10]] in hardware.<ref>{{Cite journal |last1=Schwarz |first1=E. M. |last2=Kapernick |first2=J. S. |last3=Cowlishaw |first3=M. F. |title=Decimal floating-point support on the IBM System z10 processor |doi=10.1147/JRD.2009.5388585 |journal=[[IBM Journal of Research and Development]] |volume=53 |issue=1 |pages=4:1–4:10 |date=January 2009}}</ref>

Modern IBM mainframes support three floating-point radices with 3 hexadecimal (HFP) formats, 3 binary (BFP) formats, and 3 decimal (DFP) formats. There are two floating-point units per core; one supporting HFP and BFP, and one supporting DFP; there is one register file, FPRs, which holds all 3 formats.  Starting with the [[IBM_z13_(microprocessor)|z13]] in 2015, processors have added a vector facility that includes 32 vector registers, each 128 bits wide; a vector register can contain two 64-bit or four 32-bit floating-point numbers.<ref name="pop">[http://publibfp.boulder.ibm.com/epubs/pdf/dz9zr011.pdf z/Architecture Principles of Operation]</ref>  The traditional 16 floating-point registers are overlaid on the new vector registers so some data can be manipulated with traditional floating-point instructions or with the newer vector instructions.