Editing Instruction cycle (section)

==Decode stage==
Source:<ref>{{Cite book |url=https://www.ecs.csun.edu/~cputnam/Comp546/Stallings-Appendices/19-Control_Unit.pdf |title=Control Unit Operation}}</ref>

The decoding process allows the processor to determine what instruction is to be performed so that the CPU can tell how many operands it needs to fetch in order to perform the instruction. The opcode fetched from the memory is decoded for the next steps and moved to the appropriate registers. The decoding is typically performed by [[binary decoder]]s in the CPU's CU.

=== Determining effective addresses ===
Source:<ref>{{Cite book |url=https://zeus.cs.pacificu.edu/shereen/OldCourses/cs430f08/Lectures/ch11aF08.pdf |title=Instruction Sets: Addressing Modes and Formats}}</ref>

There are various ways that an architecture can specify determining the address for operands, usually called the [[Addressing mode|addressing modes]].

Some common ways the effective address can be found are: 

* Direct addressing - the address of the instruction contains the effective address
* Indirect addressing - the address of the instruction specifies the address of the memory location that contains the effective address
* PC-relative addressing - the effective address is calculated from an address relative to the PC
* Stack addressing - the operand is at the top of the [[Stack (abstract data type)|stack]]