Editing Systolic array (section)

==Implementations==
* [[Cisco]] PXF network processor is internally organized as systolic array.<ref>{{cite web|title=Cisco 10000 Series Router Performance Routing Engine Installation|url=https://www.cisco.com/en/US/products/hw/routers/ps133/prod_installation_guide09186a0080525aba.html#wp48065|access-date=3 August 2020}}</ref>
* Google’s [[Tensor Processing Unit|TPU]] is also designed around a systolic array.
* Paracel FDF4T TestFinder text search system<ref name="FDF4">{{cite web|title=About Paracel|url=http://brandprosgroup.com/pages/first/websites/paracel/data/html/about_paracel2.html|website=brandprosgroup.com|publisher=Paracel|access-date=4 May 2018}}</ref>
* Paracel FDF4G GeneMatcher Biological (DNA and Protein) search system
* Inferentia chip at [[Amazon Web Services]]<ref>{{cite web|title=Announcing availability of Inf1 instances in Amazon SageMaker for high performance and cost-effective machine learning inference|date=14 August 2020 |url=https://aws.amazon.com/blogs/aws/amazon-ecs-now-supports-ec2-inf1-instances/|access-date=15 August 2020}}</ref>
*[[MIT Eyeriss]] is a systolic array accelerator for convolutional neural networks.<ref>{{Cite web|title=Eyeriss Project|url=http://eyeriss.mit.edu/|access-date=2021-02-21|website=eyeriss.mit.edu}}</ref><ref>{{Cite journal|last1=Chen|first1=Yu-Hsin|last2=Emer|first2=Joel|last3=Sze|first3=Vivienne|author3-link=Vivienne Sze|date=2016-10-12|title=Eyeriss: a spatial architecture for energy-efficient dataflow for convolutional neural networks|url=https://dl.acm.org/doi/10.1145/3007787.3001177|journal=ACM SIGARCH Computer Architecture News|language=en|volume=44|issue=3|pages=367–379|doi=10.1145/3007787.3001177|s2cid=3291270 |issn=0163-5964}}</ref>