Editing Transputer (section)

== Implementations ==
The first transputers were announced in 1983 and released in 1984.

In keeping with their role as [[microcontroller]]-like devices, they included on-board RAM and a built-in RAM controller which enabled more memory to be added with no added hardware. Unlike other designs, transputers did not include I/O lines: these were to be added with hardware attached to the existing serial links. There was one 'Event' line, similar to a conventional processor's interrupt line. Treated as a channel, a program could 'input' from the event channel, and proceed only after the event line was asserted.

All transputers ran from an external 5&nbsp;MHz clock input; this was multiplied to provide the processor clock.

The transputer did not include a [[memory management unit]] (MMU) or a [[virtual memory]] system.

Transputer variants (except the cancelled T9000) can be categorised into three groups: the [[16-bit computing|16-bit]] ''T2'' series, the [[32-bit computing|32-bit]] ''T4'' series, and the 32-bit ''T8'' series with 64-bit [[IEEE 754]] [[floating-point]] support.

=== T2: 16-bit ===
[[File:Inmos T225 die.JPG|thumb|150px|Inmos T225 die]]

The prototype 16-bit transputer was the ''S43'', which lacked the scheduler and DMA-controlled block transfer on the links. At launch, the ''T212'' and ''M212'' (the latter with an on-board disk controller) were the 16-bit offerings. The T212 was available in 17.5 and 20&nbsp;MHz processor clock speed ratings. The T212 was superseded by the ''T222'', with on-chip RAM expanded from 2&nbsp;KB to 4&nbsp;KB, and, later, the ''T225''. This added debugging-[[breakpoint]] support (by extending the instruction "<samp>J 0</samp>") plus some extra instructions from the T800 instruction set. Both the T222 and T225 ran at 20&nbsp;MHz.

=== T4: 32-bit ===
[[File:Inmos T425 die.JPG|thumb|150px|Inmos T425 die]]

Launched in October 1985, the ''T414'' employed the equivalent of 900,000 transistors and was fabricated with a {{nowrap|1.5 micrometre}} feature size. It was a 32-bit design, able to process 32-bit units of data and to address up to 4&nbsp;GB of main memory.<ref name="newscientist19860320_inmos">{{ cite magazine | url=https://archive.org/details/bub_gb_MZjobjexWkcC/page/n46/mode/1up | title=New chip displays its powers | magazine=New Scientist | date=20 March 1986 | access-date=22 June 2022 | last1=Anning | first1=Nick | last2=Hebditch | first2=David | pages=43–46 }}</ref> Originally, the first 32-bit variant was to be the ''T424'', but fabrication difficulties meant that this was redesigned as the T414 with 2&nbsp;KB on-board RAM instead of the intended 4&nbsp;KB. The T414 was available in 15 and 20&nbsp;MHz varieties. The RAM was later reinstated to 4&nbsp;KB on the ''T425'' (in 20, 25, and 30&nbsp;MHz varieties), which also added the <samp>J 0</samp> breakpoint support and extra T800 instructions. The ''T400'', released in September 1989, was a low-cost 20&nbsp;MHz T425 derivative with 2&nbsp;KB and two instead of four links, intended for the [[embedded system]]s market.

=== T8: floating point ===
[[File:Inmos T805 die.JPG|thumb|150px|Inmos T805 die]]

The second-generation ''T800'' transputer, introduced in 1987, had an extended instruction set. The most important addition was a 64-bit [[floating-point unit]] (FPU) and three added registers for floating point, implementing the [[IEEE 754-1985]] floating point standard. It also had 4&nbsp;KB of on-board RAM and was available in 20 or 25&nbsp;MHz versions. Breakpoint support was added in the later ''T801'' and ''T805'', the former featuring separate address and data buses to improve performance. The T805 was also later available as a 30&nbsp;MHz part.

An enhanced ''T810'' was planned, which would have had more RAM, more and faster links, extra instructions, and improved microcode, but this was cancelled around 1990.

Inmos also produced a variety of support chips for the transputer processors, such as the ''C004'' 32-way link switch and the ''C011'' and ''C012'' "link adapters" which allowed transputer links to be interfaced to an 8-bit data bus.

=== T400 ===
Part of the original Inmos strategy was to make CPUs so small and cheap that they could be combined with other logic in one device. Although a ''[[system on a chip]]'' (SoC) as they are commonly termed, are ubiquitous now, the concept was almost unheard of back in the early 1980s. Two projects were started in around 1983, the ''M212'' and the ''TV-toy''. The M212 was based on a standard T212 core with the addition of a disk controller for the ST 506 and ST 412 Shugart standards. TV-toy was to be the basis for a [[video game console]] and was joint project between Inmos and [[Sinclair Research]].

The links in the T212 and T414/T424 transputers had hardware DMA engines so that transfers could happen in parallel with execution of other processes. A variant of the design, termed the T400, not to be confused with a later transputer of the same name, was designed where the CPU handled these transfers. This reduced the size of the device considerably since 4 link engines were approximately the same size as the whole CPU. The T400 was intended to be used as a core in what were then called ''systems on silicon'' (SOS) devices, now termed and better known as ''[[system on a chip]]'' (SoC). It was this design that was to form part of TV-toy. The project was canceled in 1985.

=== T100 ===
Although the prior SoC projects had had only limited success (the M212 was sold for a time), many designers still firmly believed in the concept and in 1987, a new project, the T100 was started which combined an 8-bit version of the transputer CPU with configurable logic based on state machines. The transputer instruction set is based on 8-bit instructions and can easily be used with any word size which is a multiple of 8 bits. The target market for the T100 was to be bus controllers such as Futurebus, and an upgrade for the standard link adapters (C011 etc.). The project was stopped when the T840 (later to become the basis of the T9000) was started.

<gallery caption="T2, T4, and T8 series transputers" perrow="6">
File:KL inmos IMST212 ES.jpg|Inmos T212, PREQUAL
File:KL inmos IMST222 ES.jpg|Inmos T222, PREQUAL
File:KL STMicroelectronics_IMST225.jpg|STMicroelectronics IMST225 (Inmos T225)
File:KL inmos IMST400.jpg|Inmos T400
File:KL inmos IMST414.jpg|Inmos T414
File:KL inmos IMST425.jpg|Inmos T425
File:KL inmos IMST800 ES.jpg|Inmos T800, PREQUAL
File:KL STMicroelectronics IMST805.jpg|STMicroelectronics IMST805 (Inmos T805)
</gallery>

=== TPCORE ===
TPCORE is an implementation of the transputer, including the os-links, that runs in a [[field-programmable gate array]] (FPGA).<ref name="tanaka"/><ref>
[https://books.google.com/books?id=iDiRVk3gem0C "Communicating Process Architectures 2004"].
p. 361.
Makoto Tanaka; Naoya Fukuchi; Yutaka Ooki; and Chikara Fukunaga.
"Design of a Transputer Core and its implementation in an FPGA".
2004.
</ref>

=== T9000 ===
[[File:T9000LidOff.jpg|alt=Computer chip with lid removed showing silicon die installed at an angle|thumb|T9000 Transputer with lid removed to show silicon die]]
Inmos improved on the performance of the T8 series transputers with the introduction of the ''T9000'' (code-named ''H1'' during development). The T9000 shared most features with the T800, but moved several pieces of the design into hardware and added several features for [[superscalar]] support. Unlike the earlier models, the T9000 had a true 16&nbsp;KB high-speed [[CPU cache|cache]] (using random replacement) instead of RAM, but also allowed it to be used as memory and included MMU-like functionality to handle all of this (termed the ''PMI''). For more speed the T9000 cached the top 32 locations of the stack, instead of three as in earlier versions.
[[File:T9000Wafer.jpg|alt=Silicon wafter covered in a tiled pattern of transistors for processors reflecting sunlight in rainbow patterns|thumb|Uncut silicon wafer of Inmos T9000 transputers]]
The T9000 used a five-stage pipeline for even more speed. An interesting addition was the ''grouper''<ref>Inmos T9000 CPU patent, [http://www.freepatentsonline.com/5742783.html "US patent 5742783"],</ref> which would collect instructions out of the cache and group them into larger packages of up to 8 bytes to feed the pipeline faster. Groups then completed in one cycle, as if they were single larger instructions working on a faster CPU.

The link system was upgraded to a new 100&nbsp;MHz mode, but unlike the prior systems, the links were no longer downwardly compatible. This new packet-based link protocol was called ''DS-Link'',<ref>Inmos DS Link patent, [http://www.freepatentsonline.com/5341371.html "Communication Interface US patent 5341371"]</ref> and later formed the basis of the [[IEEE 1355]] serial interconnect standard. The T9000 also added link routing hardware called the ''VCP'' (Virtual Channel Processor) which changed the links from point-to-point to a true network, allowing for the creation of any number of ''virtual channels'' on the links. This meant programs no longer had to be aware of the physical layout of the connections. A range of DS-Link support chips were also developed, including the ''C104'' 32-way crossbar switch, and the ''C101'' link adapter.

Long delays in the T9000's development meant that the faster load/store designs were already outperforming it by the time it was to be released. It consistently failed to reach its own performance goal of beating the T800 by a factor of ten. When the project was finally cancelled it was still achieving only about 36 MIPS at 50&nbsp;MHz. The production delays gave rise to the quip that the best host architecture for a T9000 was an overhead projector.

This was too much for Inmos, which did not have the funding needed to continue development. By this time, the company had been sold to SGS-Thomson (now [[STMicroelectronics]]), whose focus was the embedded systems market, and eventually the T9000 project was abandoned. However, a comprehensively redesigned 32-bit transputer intended for embedded applications, the ''ST20'' series, was later produced, using some technology developed for the T9000. The ST20 core was incorporated into chipsets for [[set-top box]] and [[Global Positioning System]] (GPS) applications.

=== ST20 ===
Although not strictly a transputer, the ST20 was heavily influenced by the T4 and T9 and formed the basis of the T450, which was arguably the last of the transputers. The mission of the ST20 was to be a reusable core in the then emerging SoC market. The original name of the ST20 was the Reusable Micro Core (RMC). The architecture was loosely based on the original T4 architecture with a microcode-controlled data path. However, it was a full redesign, using [[VHDL]] as the design language and with an optimized (and rewritten) microcode compiler. The project was conceived as early as 1990 when it was realized that the T9 would be too big for many applications. Actual design work started in mid-1992. Several trial designs were done, ranging from a very simple RISC-style CPU with complex instructions implemented in software via traps to a rather complex superscalar design similar in concept to the [[Tomasulo algorithm]]. The final design looked very similar to the original T4 core although some simple instruction grouping and a ''workspace cache'' were added to help with performance.