Editing X86 (section)

==x86 registers==
{{Hatnote|For a description of the general notion of a CPU register, see [[Processor register]].}}

===16-bit===
The original [[Intel 8086]] and [[Intel 8088|8088]] have fourteen 16-[[bit]] registers. Four of them (AX, BX, CX, DX) are general-purpose registers (GPRs), although each may have an additional purpose; for example, only CX can be used as a counter with the loop instruction. Each can be accessed as two separate bytes (thus BX's high byte can be accessed as BH and low byte as BL). Two pointer registers have special roles: SP (stack pointer) points to the "top" of the [[stack (data structure)|stack]], and BP (base pointer) is often used to point at some other place in the stack, typically above the local variables (see [[frame pointer]]). The registers SI, DI, BX and BP are [[address register]]s, and may also be used for array indexing.

One of four possible 'segment registers' (CS, DS, SS and ES) is used to form a memory address. In the original 8086 / 8088 / 80186 / 80188 every address was built from a segment register and one of the general purpose registers. For example ds:si is the notation for an address formed as [16 * ds + si] to allow 20-bit addressing rather than 16 bits, although this changed in later processors. At that time only certain combinations were supported.

The [[FLAGS register (computing)|FLAGS register]] contains [[Flag (computing)|flag]]s such as [[carry flag]], [[overflow flag]] and [[zero flag]]. Finally, the [[instruction pointer]] (IP) points to the next instruction that will be fetched from memory and then executed; this register cannot be directly accessed (read or written) by a program.<ref>{{cite web |url=http://www.cs.virginia.edu/~evans/cs216/guides/x86.html |title=Guide to x86 Assembly |publisher=Cs.virginia.edu |date=September 11, 2013 |access-date=February 6, 2014 |archive-date=March 24, 2020 |archive-url=https://web.archive.org/web/20200324154938/http://www.cs.virginia.edu/~evans/cs216/guides/x86.html |url-status=live }}</ref>

The [[Intel 80186]] and [[Intel 80188|80188]] are essentially an upgraded 8086 or 8088 CPU, respectively, with on-chip peripherals added, and they have the same CPU registers as the 8086 and 8088 (in addition to interface registers for the peripherals).

The 8086, 8088, 80186, and 80188 can use an optional floating-point coprocessor, the [[Intel 8087|8087]]. The 8087 appears to the programmer as part of the CPU and adds eight 80-bit wide registers, st(0) to st(7), each of which can hold numeric data in one of seven formats: 32-, 64-, or 80-bit floating point, 16-, 32-, or 64-bit (binary) integer, and 80-bit packed decimal integer.<ref name="i86"/>{{rp|S-6, S-13..S-15}} It also has its own 16-bit status register accessible through the {{mono|fstsw}} instruction, and it is common to simply use some of its bits for branching by copying it into the normal FLAGS.<ref>{{cite web |title=FSTSW/FNSTSW — Store x87 FPU Status Word |url=https://www.felixcloutier.com/x86/fstsw:fnstsw |quote=The FNSTSW AX form of the instruction is used primarily in conditional branching... |access-date=January 15, 2020 |archive-date=January 25, 2022 |archive-url=https://web.archive.org/web/20220125121653/https://www.felixcloutier.com/x86/fstsw:fnstsw |url-status=live }}</ref>

In the [[Intel 80286]], to support [[protected mode]], three special registers hold descriptor table addresses (GDTR, LDTR, [[Interrupt descriptor table|IDTR]]), and a fourth task register (TR) is used for task switching. The [[Intel 80287|80287]] is the floating-point coprocessor for the 80286 and has the same registers as the 8087 with the same data formats.

===32-bit===
[[File:Table of x86 Registers svg.svg|thumb|upright=2.2|Registers available in the x86-64 instruction set]]

With the advent of the 32-bit [[Intel 80386|80386]] processor, the 16-bit general-purpose registers, base registers, index registers, instruction pointer, and [[FLAGS register]], but not the segment registers, were expanded to 32&nbsp;bits. The nomenclature represented this by prefixing an "'''E'''" (for "extended") to the register names in [[x86 assembly language]]. Thus, the AX register corresponds to the lower 16&nbsp;bits of the new 32-bit EAX register, SI corresponds to the lower 16&nbsp;bits of ESI, and so on. The general-purpose registers, base registers, and index registers can all be used as the base in addressing modes, and all of those registers except for the stack pointer can be used as the index in addressing modes.

Two new segment registers (FS and GS) were added. With a greater number of registers, instructions and operands, the [[machine code]] format was expanded. To provide backward compatibility, segments with executable code can be marked as containing either 16-bit or 32-bit instructions. Special prefixes allow inclusion of 32-bit instructions in a 16-bit segment or vice versa.

The 80386 had an optional floating-point coprocessor, the [[80387]]; it had eight 80-bit wide registers: st(0) to st(7),<ref>{{cite book|url= http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf|title= Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture|at= Chapter 8|publisher= Intel|date= March 2013|access-date= April 23, 2013|archive-date= April 2, 2013|archive-url= https://web.archive.org/web/20130402233513/http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf|url-status= live}}</ref> like the 8087 and 80287. The 80386 could also use an 80287 coprocessor.<ref>{{cite web|url=http://www.cpu-world.com/CPUs/80287/|title=Intel 80287 family|website=CPU-world|access-date=July 21, 2016|archive-date=August 9, 2016|archive-url=https://web.archive.org/web/20160809185320/http://www.cpu-world.com/CPUs/80287/|url-status=live}}</ref> With the [[80486]] and all subsequent x86 models, the floating-point processing unit (FPU) is integrated on-chip.

The [[Pentium MMX]] added eight 64-bit [[MMX (instruction set)|MMX]] integer vector registers (MM0 to MM7, which share lower bits with the 80-bit-wide FPU stack).<ref>{{cite book|url= http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf|title= Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture|at= Chapter 9|publisher= Intel|date= March 2013|access-date= April 23, 2013|archive-date= April 2, 2013|archive-url= https://web.archive.org/web/20130402233513/http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf|url-status= live}}</ref> With the [[Pentium III]], Intel added a 32-bit [[Streaming SIMD Extensions]] (SSE) control/status register (MXCSR) and eight 128-bit SSE floating-point registers (XMM0 to XMM7).<ref>{{cite book
|url= http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf
|title= Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture
|at= Chapter 10
|publisher= Intel
|date= March 2013
|access-date= April 23, 2013
|archive-date= April 2, 2013
|archive-url= https://web.archive.org/web/20130402233513/http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf
|url-status= live
}}</ref>

===64-bit===
{{Further|x86-64}}
Starting with the [[AMD Opteron]] processor, the x86 architecture extended the 32-bit registers into 64-bit registers in a way similar to how the 16 to 32-bit extension took place. An '''R'''-prefix (for "register") identifies the 64-bit registers (RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, RFLAGS, RIP), and eight additional 64-bit general registers (R8–R15) were also introduced in the creation of [[x86-64]]. Also, eight more SSE vector registers (XMM8–XMM15) were added. However, these extensions are only usable in 64-bit mode, which is one of the two modes only available in [[long mode]]. The addressing modes were not dramatically changed from 32-bit mode, except that addressing was extended to 64&nbsp;bits, virtual addresses are now sign extended to 64&nbsp;bits (in order to disallow mode bits in virtual addresses), and other selector details were dramatically reduced. In addition, an addressing mode was added to allow memory references relative to RIP (the [[instruction pointer]]), to ease the implementation of [[position-independent code]], used in shared libraries in some operating systems.

===128-bit===
{{See also|Streaming SIMD Extensions#Registers}}
SIMD registers XMM0–XMM15 (XMM0–XMM31 when [[AVX-512]] is supported).

===256-bit===
{{See also|Advanced Vector Extensions#New features}}
SIMD registers YMM0–YMM15 (YMM0–YMM31 when [[AVX-512]] is supported). Lower half of each of the YMM registers maps onto the corresponding XMM register.

===512-bit===
{{See also|Advanced Vector Extensions#AVX-512}}
SIMD registers ZMM0–ZMM31. Lower half of each of the ZMM registers maps onto the corresponding YMM register.

===Miscellaneous/special purpose===
x86 processors that have a [[protected mode]], i.e. the 80286 and later processors, also have three descriptor registers (GDTR, LDTR, [[Interrupt descriptor table|IDTR]]) and a task register (TR).

32-bit x86 processors (starting with the 80386) also include various special/miscellaneous registers such as [[control register]]s (CR0 through 4, CR8 for 64-bit only), [[debug register]]s (DR0 through 3, plus 6 and 7), [[test register]]s (TR3 through 7; 80486 only), and [[model-specific register]]s (MSRs, appearing with the Pentium{{Efn|Two MSRs of particular interest are SYSENTER_EIP_MSR<!-- (0x176) --> and SYSENTER_ESP_MSR<!-- (0x175) -->, introduced on the Pentium® II processor, which store the address of the kernel mode system service handler<!-- nt!KiFastCallEntry --> and corresponding kernel stack pointer. Initialized during system startup, SYSENTER_EIP_MSR and SYSENTER_ESP_MSR are used by the SYSENTER (Intel) or SYSCALL (AMD) instructions to achieve Fast System Calls, about three times faster<!-- http://www.codeguru.com/cpp/misc/misc/system/article.php/c8223/System-Call-Optimization-with-the-SYSENTER-Instruction.htm 266% as fast (166% faster) on a PIII Dual 800 MHz --> than the software interrupt method used previously.}}).

[[AVX-512]] has eight extra 64-bit mask registers K0–K7 for selecting elements in a vector register. Depending on the vector register and element widths, only a subset of bits of the mask register may be used by a given instruction.

===Purpose===
Although the main registers (with the exception of the instruction pointer) are "general-purpose" in the 32-bit and 64-bit versions of the instruction set and can be used for anything, it was originally envisioned that they be used for the following purposes:
* AL/AH/AX/EAX/RAX: Accumulator
* CL/CH/CX/ECX/RCX: Counter (for use with loops and strings)
* DL/DH/DX/EDX/RDX: Extend the precision of the accumulator (e.g. combine 32-bit EAX and EDX for 64-bit integer operations in 32-bit code)
* BL/BH/BX/EBX/RBX: Base index (for use with arrays)
* SP/ESP/RSP: Stack pointer for top address of the stack.
* BP/EBP/RBP: Stack base pointer for holding the address of the current [[stack frame]].
* SI/ESI/RSI: ''Source index'' for [[string (computer science)|string]] operations.
* DI/EDI/RDI: ''Destination index'' for string operations.
* IP/EIP/RIP: Instruction pointer. Holds the [[program counter]], the address of next instruction.

Segment registers:
*CS: Code
*DS: Data
*SS: Stack
*ES: Extra data
*FS: Extra data #2
*GS: Extra data #3

No particular purposes were envisioned for the other 8 registers available only in 64-bit mode.

Some instructions compile and execute more efficiently when using these registers for their designed purpose. For example, using AL as an [[Accumulator (computing)|accumulator]] and adding an immediate byte value to it produces the efficient ''add to AL'' [[opcode]] of 04h, whilst using the BL register produces the generic and longer ''add to register'' opcode of 80C3h. Another example is double precision division and multiplication that works specifically with the AX and DX registers.

Modern compilers benefited from the introduction of the ''sib'' byte (''scale-index-base byte'') that allows registers to be treated uniformly ([[minicomputer]]-like). However, using the sib byte universally is non-optimal, as it produces longer encodings than only using it selectively when necessary. (The main benefit of the sib byte is the orthogonality and more powerful addressing modes it provides, which make it possible to save instructions and the use of registers for address calculations such as scaling an index.) Some special instructions lost priority in the hardware design and became slower than equivalent small code sequences. A notable example is the LODSW instruction.

===Structure===
{| class="wikitable"
|+ General Purpose Registers (A, B, C and D)
! style="width:50pt;"| 64
! style="width:50pt;"| 56
! style="width:50pt;"| 48
! style="width:50pt;"| 40
! style="width:50pt;"| 32
! style="width:50pt;"| 24
! style="width:50pt;"| 16
! style="width:50pt;"| 8
|-
| colspan="8" style="text-align:center;"| R?X
|-
| colspan="4" style="background:lightgrey" |
| colspan="4" style="text-align:center;"| E?X
|-
| colspan="6" style="background:lightgrey" |
| colspan="2" style="text-align:center;"| ?X
|-
| colspan="6" style="background:lightgrey" |
| style="text-align:center;"| ?H
| style="text-align:center;"| ?L
|}

{| class="wikitable"
|+ 64-bit mode-only General Purpose Registers (R8, R9, R10, R11, R12, R13, R14, R15)
! style="width:50pt;"| 64
! style="width:50pt;"| 56
! style="width:50pt;"| 48
! style="width:50pt;"| 40
! style="width:50pt;"| 32
! style="width:50pt;"| 24
! style="width:50pt;"| 16
! style="width:50pt;"| 8
|-
| colspan="8" style="text-align:center;"| ?
|-
| colspan="4" style="background:lightgrey" |
| colspan="4" style="text-align:center;"| ?D
|-
| colspan="6" style="background:lightgrey" |
| colspan="2" style="text-align:center;"| ?W
|-
| colspan="7" style="background:lightgrey" |
| style="text-align:center;"| ?B
|}

{| class="wikitable"
|+ Segment Registers (C, D, S, E, F and G)
! style="width:50pt;"| 16
! style="width:50pt;"| 8
|-
| colspan="2" style="text-align:center;"| ?S
|}

{| class="wikitable"
|+ Pointer Registers (S and B)
! style="width:50pt;"| 64
! style="width:50pt;"| 56
! style="width:50pt;"| 48
! style="width:50pt;"| 40
! style="width:50pt;"| 32
! style="width:50pt;"| 24
! style="width:50pt;"| 16
! style="width:50pt;"| 8
|-
| colspan="8" style="text-align:center;"| R?P
|-
| colspan="4" style="background:lightgrey" |
| colspan="4" style="text-align:center;"|E?P
|-
| colspan="6" style="background:lightgrey" |
| colspan="2" style="text-align:center;"|?P
|-
| colspan="7" style="background:lightgrey" |
| style="text-align:center;"| ?PL
|}
Note: The ?PL registers are only available in 64-bit mode.

{| class="wikitable"
|+ Index Registers (S and D)
! style="width:50pt;"| 64
! style="width:50pt;"| 56
! style="width:50pt;"| 48
! style="width:50pt;"| 40
! style="width:50pt;"| 32
! style="width:50pt;"| 24
! style="width:50pt;"| 16
! style="width:50pt;"| 8
|-
| colspan="8" style="text-align:center;"| R?I
|-
| colspan="4" style="background:lightgrey" |
| colspan="4" style="text-align:center;"| E?I
|-
| colspan="6" style="background:lightgrey" |
| colspan="2" style="text-align:center;"| ?I
|-
| colspan="7" style="background:lightgrey" |
| style="text-align:center;"| ?IL
|}
Note: The ?IL registers are only available in 64-bit mode.

{| class="wikitable"
|+ Instruction Pointer Register (I)
! style="width:50pt;"| 64
! style="width:50pt;"| 56
! style="width:50pt;"| 48
! style="width:50pt;"| 40
! style="width:50pt;"| 32
! style="width:50pt;"| 24
! style="width:50pt;"| 16
! style="width:50pt;"| 8
|-
| colspan="8" style="text-align:center;"| RIP
|-
| colspan="4" style="background:lightgrey" |
| colspan="4" style="text-align:center;"| EIP
|-
| colspan="6" style="background:lightgrey" |
| colspan="2" style="text-align:center;"| IP
|}