Editing Canonical normal form (section)

===Top-down vs. bottom-up design===
We have now seen how the minterm/maxterm tools can be used to design an adder stage in canonical form with the addition of some Boolean algebra, costing just 2 gate delays for each of the outputs. That's the "top-down" way to design the digital circuit for this function, but is it the best way? The discussion has focused on identifying "fastest" as "best," and the augmented canonical form meets that criterion flawlessly, but sometimes other factors predominate. The designer may have a primary goal of minimizing the number of gates, and/or of minimizing the fanouts of signals to other gates since big fanouts reduce resilience to a degraded power supply or other environmental factors. In such a case, a designer may develop the canonical-form design as a baseline, then try a bottom-up development, and finally compare the results.

The bottom-up development involves noticing that ''u = ci'' XOR (''x'' XOR ''y''), where XOR means eXclusive OR [true when either input is true but not when both are true], and that ''co'' = ''ci x'' + ''x y'' + ''y ci''. One such development takes twelve NOR gates in all: six 2-input gates and two 1-input gates to produce ''u'' in 5 gate delays, plus three 2-input gates and one 3-input gate to produce ''co''&prime; in 2 gate delays. The canonical baseline took eight 3-input NOR gates plus three 4-input NOR gates to produce ''u, co'' and ''co''&prime; in 2 gate delays. If the circuit inventory actually includes 4-input NOR gates, the top-down canonical design looks like a winner in both gate count and speed. But if (contrary to our convenient supposition) the circuits are actually 3-input NOR gates, of which two are required for each 4-input NOR function, then the canonical design takes 14 gates compared to 12 for the bottom-up approach, but still produces the sum digit ''u'' considerably faster.  The fanout comparison is tabulated as:
{| class="wikitable" style="margin: 1em auto 1em auto"
!width="50"|Variables
!width="50"|Top-down
!width="50"|Bottom-up
|-
! x
|4||1
|-
! x'
|4||3
|-
! y
|4||1
|-
! y'
|4||3
|-
! ci
|4||1
|-
! ci'
|4||3
|-
! M or m
|4@1,4@2||N/A
|-
! x XOR y
|N/A||2
|-
! Misc
|N/A||5@1
|-
! Max
|4||3
|}
The description of the bottom-up development mentions ''co''&prime; as an output but not ''co''.  Does that design simply never need the direct form of the carry out? Well, yes and no. At each stage, the calculation of ''co''&prime; depends only on ''ci''&prime;, ''x''&prime; and ''y''&prime;, which means that the carry propagation ripples along the bit positions just as fast as in the canonical design without ever developing ''co''. The calculation of ''u'', which does require ''ci'' to be made from ''ci''&prime; by a 1-input NOR, is slower but for any word length the design only pays that penalty once (when the leftmost sum digit is developed). That's because those calculations overlap, each in what amounts to its own little pipeline without affecting when the next bit position's sum bit can be calculated. And, to be sure, the ''co''&prime; out of the leftmost bit position will probably have to be complemented as part of the logic determining whether the addition overflowed. But using 3-input NOR gates, the bottom-up design is very nearly as fast for doing parallel addition on a non-trivial word length, cuts down on the gate count, and uses lower fanouts ... so it wins if gate count and/or fanout are paramount!

We'll leave the exact circuitry of the bottom-up design of which all these statements are true as an exercise for the interested reader, assisted by one more algebraic formula: ''u'' = ''ci''(''x'' XOR ''y'') + ''ci''&prime;(''x'' XOR ''y'')&prime;]&prime;. Decoupling the carry propagation from the sum formation in this way is what elevates the performance of a ''carry-lookahead adder'' over that of a ''ripple carry adder''.