Editing Digital Visual Interface (section)

===Digital===
* Minimum TMDS clock frequency: 25.175&nbsp;MHz
** Used for the mandatory "low pixel format" display mode: [[VGA (resolution)|VGA]] (640x480) @ 60&nbsp;Hz
* Maximum single link TMDS clock frequency: 165&nbsp;MHz
* Single link maximum [[gross bit rate]] (including 8b/10b overhead): 4.95&nbsp;Gbit/s
** [[Net bit rate]] (subtracting 8b/10b overhead): 3.96&nbsp;Gbit/s
* Dual link bit rates are twice that of single link at an identical clock frequency.
** Gross bit rate (Including 8b/10b overhead) at a 165&nbsp;MHz clock: 9.90&nbsp;Gbit/s.
*** Net bit rate (subtracting 8b/10b overhead): 7.92&nbsp;Gbit/s
** Clocks above 165&nbsp;MHz are allowed in dual link mode{{notetag|and only used when total bandwidth requirement surpassing 330MHz TMDS clock. The specification only specifies first link to operate at above single-link maximum in such scenario.<ref name=DVI1.0 />{{rp|§2.2.2.}}}}
* Bits per pixel:
** 24 bits per pixel support is mandatory in all resolutions supported.
** Less than 24 bits per pixel is optional.
** Dual link optionally supports up to 48 bits per pixel.
*** If a depth greater than 24 bits per pixel is desired, the least significant bits are sent on the second link.
* Pixels per TMDS clock cycle:
** 1 (single link at 24 bits or less per pixel, and dual link for 25 to 48 bits per pixel) or
** 2 (dual link at 24 bits or less per pixel)
* Example display modes (''single link''):
** [[SXGA]] ({{resx|1280|1024}}) @ 85&nbsp;Hz with GTF blanking (159&nbsp;MHz TMDS clock)
** [[FHD]] ({{resx|1920|1080}}) @ 60&nbsp;Hz with CVT-RB blanking (139&nbsp;MHz TMDS clock)
** [[UXGA]] ({{resx|1600|1200}}) @ 60&nbsp;Hz with GTF blanking (161&nbsp;MHz TMDS clock)
** [[WUXGA]] ({{resx|1920|1200}}) @ 60&nbsp;Hz with CVT-RB blanking (154&nbsp;MHz TMDS clock)
** [[WQXGA]] ({{resx|2560|1600}}) @ 30&nbsp;Hz with CVT-RB blanking (132&nbsp;MHz TMDS clock)
*Example display modes (''dual link''):
** [[QXGA]] ({{resx|2048|1536}}) @ 72&nbsp;Hz with CVT blanking (2 pixels per 163&nbsp;MHz TMDS clock)
** [[FHD]] ({{resx|1920|1080}}) @ 144&nbsp;Hz<ref>{{Cite web |date=2019-08-21 |title=The Best DVI Cable for 144hz {{!}} The Technology Land |url=https://thetechnologyland.com/the-best-dvi-cable-for-144hz/ |access-date=2022-07-14 |website=thetechnologyland.com |language=en-US}}</ref>
** [[WUXGA]] ({{resx|1920|1200}}) @ 120&nbsp;Hz with CVT-RB blanking (2 pixels per 154&nbsp;MHz TMDS clock)
** [[WQXGA]] ({{resx|2560|1600}}) @ 60&nbsp;Hz with CVT-RB blanking (2 pixels per 135&nbsp;MHz TMDS clock)
** [[WQUXGA]] ({{resx|3840|2400}}) @ 30&nbsp;Hz with CVT-RB blanking (2 pixels per 146&nbsp;MHz TMDS clock)

[[Generalized Timing Formula]] (GTF) is a [[VESA]] standard which can easily be calculated with the [[Linux]] gtf utility. [[Coordinated Video Timings]]-Reduced Blanking (CVT-RB) is a [[VESA]] standard which offers reduced horizontal and vertical blanking for non-CRT based displays.<ref>{{cite news |url=https://www.nvidia.com/object/advanced_timings.html |title=Advanced Timing and CEA/EIA-861B Timings |publisher=NVIDIA |access-date=2008-06-18}}</ref>

====Digital data encoding====
One of the purposes of DVI stream encoding is to provide a [[DC-balanced]] output that reduces decoding errors. This goal is achieved by using 10-bit symbols for 8-bit or less characters and using the extra bits for the DC balancing.

Like other ways of transmitting video, there are two different regions: the active region, where pixel data is sent, and the control region, where synchronization signals are sent. The active region is encoded using [[transition-minimized differential signaling]], where the control region is encoded with a fixed [[8b/10b encoding]]. As the two schemes yield different 10-bit symbols, a receiver can fully differentiate between active and control regions.

When DVI was designed, most computer monitors were still of the [[cathode-ray tube]] type that require analog video synchronization signals. The timing of the digital synchronization signals matches the equivalent analog ones, so the process of transforming DVI to and from an analog signal does not require extra (high-speed) memory, expensive at the time.

[[High-bandwidth Digital Content Protection|HDCP]] is an extra layer that transforms the 10-bit symbols before transmitting. Only after correct authorization can the receiver undo the HDCP encryption. Control regions are not encrypted in order to let the receiver know when the active region starts.

====Clock and data relationship====
DVI provide one TMDS clock pair and 3 TMDS data pairs in single link mode or 6 TMDS data pairs in dual link mode. TMDS data pairs operate at a [[gross bit rate]] that is 10 times the frequency of the TMDS clock. In each TMDS clock period there is a 10-bit symbol per TMDS data pair representing 8-bits of pixel color. In single link mode each set of three 10-bit symbols represents one 24-bit pixel, while in dual link mode each set of six 10-bit symbols either represents two 24-bit pixels or one pixel of up to 48-bit [[color depth]].

The specification document allows the data and the clock to not be aligned. However, as the ratio between the TMDS clock and gross bit rate per TMDS pair is fixed at 1:10, the unknown alignment is kept over time. The receiver must recover the bits on the stream using any of the techniques of [[clock recovery|clock/data recovery]] to find the correct symbol boundary. The DVI specification allows the TMDS clock to vary between 25&nbsp;MHz and 165&nbsp;MHz. This 1:6.6 ratio can make clock recovery difficult, as [[phase-locked loop]]s, if used, need to work over a large frequency range. One benefit of DVI over other interfaces is that it is relatively straightforward to transform the signal from the digital domain into the analog domain using a video [[Digital-to-analog converter|DAC]], as both clock and synchronization signals are transmitted. Fixed frequency interfaces, like [[DisplayPort]], need to reconstruct the clock from the transmitted data.

====Display power management====
The DVI specification includes signaling for reducing power consumption. Similar to the analog [[VESA Display Power Management Signaling|VESA display power management signaling]] <!-- didn't think this was a proper noun, so is not capitalized.  However, the referenced page did capitalize it, and think the page should be moved.  I guess, feel free to remove the text after the bar if you think it should be capitalized.  --> (DPMS) standard, a connected device can turn a monitor off when the connected device is powered down, or programmatically if the display controller of the device supports it. Devices with this capability can also attain Energy Star certification.