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Instruction set architecture
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====Number of operands==== Instruction sets may be categorized by the maximum number of operands ''explicitly'' specified in instructions. (In the examples that follow, ''a'', ''b'', and ''c'' are (direct or calculated) addresses referring to memory cells, while ''reg1'' and so on refer to machine registers.) C = A+B *0-operand (''zero-address machines''), so called [[stack machine]]s: All arithmetic operations take place using the top one or two positions on the stack:{{Sfn|Hennessy|Patterson|2003|p=92}} <code>push a</code>, <code>push b</code>, <code>add</code>, <code>pop c</code>. **<code>C = A+B</code> needs ''four instructions''.{{Sfn|Hennessy|Patterson|2003|p=93}} For stack machines, the terms "0-operand" and "zero-address" apply to arithmetic instructions, but not to all instructions, as 1-operand push and pop instructions are used to access memory. *1-operand (''one-address machines''), so called [[accumulator machine]]s, include early computers and many small [[microcontroller]]s: most instructions specify a single right operand (that is, constant, a register, or a memory location), with the implicit [[accumulator (computing)|accumulator]] as the left operand (and the destination if there is one): <code>load a</code>, <code>add b</code>, <code>store c</code>. **<code>C = A+B</code> needs ''three instructions''.{{Sfn|Hennessy|Patterson|2003|p=93}} *2-operand β many CISC and RISC machines fall under this category: **CISC β <code>move A</code> to ''C''; then <code>add B</code> to ''C''. ***<code>C = A+B</code> needs ''two instructions''. This effectively 'stores' the result without an explicit ''store'' instruction. **CISC β Often machines are [https://web.archive.org/web/20131105155703/http://cs.smith.edu/~thiebaut/ArtOfAssembly/CH04/CH04-3.html#HEADING3-79 limited to one memory operand] per instruction: <code>load a,reg1</code>; <code>add b,reg1</code>; <code>store reg1,c</code>; This requires a load/store pair for any memory movement regardless of whether the <code>add</code> result is an augmentation stored to a different place, as in <code>C = A+B</code>, or the same memory location: <code>A = A+B</code>. ***<code>C = A+B</code> needs ''three instructions''. **RISC β Requiring explicit memory loads, the instructions would be: <code>load a,reg1</code>; <code>load b,reg2</code>; <code>add reg1,reg2</code>; <code>store reg2,c</code>. ***<code>C = A+B</code> needs ''four instructions''. *3-operand, allowing better reuse of data:<ref name="Cocke"> {{Cite journal |last1=Cocke |first1=John |last2=Markstein |first2=Victoria |date=January 1990 |title=The evolution of RISC technology at IBM |url=https://www.cis.upenn.edu/~milom/cis501-Fall11/papers/cocke-RISC.pdf |journal=IBM Journal of Research and Development |volume=34 |issue=1 |pages=4β11 |doi=10.1147/rd.341.0004 |access-date=2022-10-05}} </ref> **CISC β It becomes either a single instruction: <code>add a,b,c</code> ***<code>C = A+B</code> needs ''one instruction''. **CISC β Or, on machines limited to two memory operands per instruction, <code>move a,reg1</code>; <code>add reg1,b,c</code>; ***<code>C = A+B</code> needs ''two instructions''. **RISC β arithmetic instructions use registers only, so explicit 2-operand load/store instructions are needed: <code>load a,reg1</code>; <code>load b,reg2</code>; <code>add reg1+reg2->reg3</code>; <code>store reg3,c</code>; ***<code>C = A+B</code> needs ''four instructions''. ***Unlike 2-operand or 1-operand, this leaves all three values a, b, and c in registers available for further reuse.<ref name=Cocke/> *more operandsβsome CISC machines permit a variety of addressing modes that allow more than 3 operands (registers or memory accesses), such as the [[VAX]] "POLY" polynomial evaluation instruction. Due to the large number of bits needed to encode the three registers of a 3-operand instruction, RISC architectures that have 16-bit instructions are invariably 2-operand designs, such as the Atmel AVR, [[TI MSP430]], and some versions of [[ARM Thumb]]. RISC architectures that have 32-bit instructions are usually 3-operand designs, such as the [[ARM architecture family|ARM]], [[AVR32]], [[MIPS architecture|MIPS]], [[Power ISA]], and [[SPARC]] architectures. Each instruction specifies some number of operands (registers, memory locations, or immediate values) ''explicitly''. Some instructions give one or both operands implicitly, such as by being stored on top of the [[stack (data structure)|stack]] or in an implicit register. If some of the operands are given implicitly, fewer operands need be specified in the instruction. When a "destination operand" explicitly specifies the destination, an additional operand must be supplied. Consequently, the number of operands encoded in an instruction may differ from the mathematically necessary number of arguments for a logical or arithmetic operation (the [[arity]]). Operands are either encoded in the "opcode" representation of the instruction, or else are given as values or addresses following the opcode.
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