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Itanium
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=== Itanium 9500 (Poulson): 2012 === Intel first mentioned Poulson on March 1, 2005, at the Spring [[Intel Developer Forum|IDF]].<ref>{{cite web |title=Intel Platforms, Technologies To Drive Enterprise Advances |url=https://www.intel.com/pressroom/archive/releases/2005/20050301corp_a.htm |publisher=Intel |access-date=31 March 2022}}</ref> In June 2007 Intel said that Poulson would use a [[32 nanometer|32 nm]] process technology, skipping the [[45 nanometer|45 nm]] process.<ref name="mercury"/> This was necessary for catching up after Itanium's delays left it at [[90 nm]] competing against [[65 nm]] and [[45 nm]] processors. At [[International Solid-State Circuits Conference|ISSCC]] 2011, Intel presented a paper called "A 32nm 3.1 Billion Transistor 12-Wide-Issue Itanium Processor for Mission Critical Servers."<ref name="dx.doi.org"/><ref>{{cite web |url = http://isscc.org/wp-content/uploads/sites/10/2017/05/ISSCC2011_AdvanceProgram.pdf |title = ISSCC 2011 |access-date = November 17, 2017 |archive-date = December 1, 2017 |archive-url = https://web.archive.org/web/20171201034615/http://isscc.org/wp-content/uploads/sites/10/2017/05/ISSCC2011_AdvanceProgram.pdf |url-status = dead }}</ref> Analyst David Kanter speculated that Poulson would use a new microarchitecture, with a more advanced form of multithreading that uses up to two threads, to improve performance for single threaded and multithreaded workloads.<ref>{{cite web | url=https://www.realworldtech.com/poulson-preview/ | title=New Itanium Microarchitecture at ISSCC 2011 | access-date=July 4, 2023 | last=Kanter | first=David | date=November 17, 2010 | work=Real World Tech }}</ref> Some information was also released at the [[Hot Chips]] conference.<ref>{{cite web |url = https://itpeernetwork.intel.com/itanium-poulson-update-greater-parallelism-new-instruction-replay-more-catch-the-details-from-hotchips/ |title = Itanium Poulson Update — Greater Parallelism, New Instruction Replay & More: Catch the details from Hotchips! |date = August 19, 2011 |access-date = November 17, 2017 |archive-date = June 27, 2018 |archive-url = https://web.archive.org/web/20180627144340/https://itpeernetwork.intel.com/itanium-poulson-update-greater-parallelism-new-instruction-replay-more-catch-the-details-from-hotchips/ |url-status = live }}</ref><ref>{{cite web | url=http://www.slideshare.net/PaulineNist/intel-itanium-poulson-update-at-hotchips | title=Intel Itanium Hotchips 2011 Overview | date=18 August 2011 | access-date=January 23, 2012 | archive-date=14 February 2012 | archive-url=https://web.archive.org/web/20120214131459/http://www.slideshare.net/PaulineNist/intel-itanium-poulson-update-at-hotchips | url-status=live }}</ref> Information presented improvements in multithreading, resiliency improvements ([[Intel Instruction Replay]] RAS) and few new instructions (thread priority, integer instruction, cache prefetching, and data access hints). Poulson was released on November 8, 2012, as the '''Itanium 9500''' series processor. It is the follow-on processor to Tukwila. It features eight cores and has a 12-wide issue architecture, multithreading enhancements, and new instructions to take advantage of parallelism, especially in virtualization.<ref name="Kittson"/><ref name="poulson-the-future-of-itanium-servers">{{cite web | url=https://www.realworldtech.com/poulson/ | last=Kanter | first=David | title=Poulson: The Future of Itanium Servers | publisher=Real World Tech | date=May 18, 2011 | access-date=November 9, 2012 | archive-url=https://web.archive.org/web/20121102093620/http://www.realworldtech.com/poulson/ | archive-date=November 2, 2012 | url-status=live }}</ref><ref name="HotChip-Poulson">{{cite web |url = http://newsroom.intel.com/servlet/JiveServlet/download/38-5835/Hot%20Chips%20%20Poulson%20disclosure%20Factsheet.pdf |title = Hot Chips Poulson Disclosure Factsheet |access-date = August 19, 2011 |date = August 19, 2011 |work = Intel press release |archive-url = https://web.archive.org/web/20120324101540/http://newsroom.intel.com/servlet/JiveServlet/download/38-5835/Hot%20Chips%20%20Poulson%20disclosure%20Factsheet.pdf |archive-date = March 24, 2012 |url-status = dead |df = mdy-all }}</ref> The Poulson L3 cache size is 32 MB and common for all cores, not divided like previously. L2 cache size is 6 MB, 512 I [[Kibibyte|KB]], 256 D KB per core.<ref name="dx.doi.org">{{cite conference | chapter=A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers | date=February 24, 2011 |doi = 10.1109/ISSCC.2011.5746230|conference = 2011 IEEE International Solid-State Circuits Conference|pages = 84–86|last1 = Riedlinger|first1 = Reid J.|last2 = Bhatia|first2 = Rohit|last3 = Biro|first3 = Larry|last4 = Bowhill|first4 = Bill|last5 = Fetzer|first5 = Eric|last6 = Gronowski|first6 = Paul|last7 = Grutkowski|first7 = Tom| title=2011 IEEE International Solid-State Circuits Conference |isbn = 978-1-61284-303-2}}</ref> Die size is 544 mm², less than its predecessor Tukwila (698.75 mm²).<ref>{{cite magazine | url=https://www.eetimes.com/researchers-carve-cpu-into-plastic-foil/ | title=Researchers carve CPU into plastic foil | first=Rick | last=Merrit | date=November 23, 2010 | magazine=EE Times | access-date=December 17, 2019 | archive-date=December 17, 2019 | archive-url=https://web.archive.org/web/20191217201623/https://www.eetimes.com/researchers-carve-cpu-into-plastic-foil/ | url-status=live }}</ref><ref>{{cite web | url=https://www.engadget.com/2011/08/22/intel-talks-up-next-gen-itanium-32nm-8-core-poulson/ | title=Intel talks up next-gen Itanium: 32nm, 8-core Poulson | first=Terrence | last=O'Brien | publisher=[[Engadget]] | date=August 22, 2011 | access-date=April 30, 2012 | archive-date=April 21, 2018 | archive-url=https://web.archive.org/web/20180421163456/https://www.engadget.com/2011/08/22/intel-talks-up-next-gen-itanium-32nm-8-core-poulson/ | url-status=live }}</ref> Intel's Product Change Notification (PCN) 111456-01 lists four models of Itanium 9500 series [[central processing unit|CPU]], which was later removed in a revised document.<ref name="cpu-world.com">{{cite web| url = http://www.cpu-world.com/news_2012/2012061301_Unreleased_Intel_Itanium_9500-series_CPUs_spotted.html| title = Unreleased Intel Itanium 9500-series CPUs spotted| access-date = 2012-08-02| archive-date = 2017-11-22| archive-url = https://web.archive.org/web/20171122032035/http://www.cpu-world.com/news_2012/2012061301_Unreleased_Intel_Itanium_9500-series_CPUs_spotted.html| url-status = live}}</ref> The parts were later listed in Intel's Material Declaration Data Sheets (MDDS) database.<ref>{{cite web| url = http://www.cpu-world.com/news_2012/2012062601_Spotted_9500-series_CPUs_confirmed_to_be_Poulson_Itaniums.html| title = Spotted 9500-series CPUs confirmed to be "Poulson" Itaniums| access-date = 2012-08-02| archive-date = 2017-10-06| archive-url = https://web.archive.org/web/20171006152039/http://www.cpu-world.com/news_2012/2012062601_Spotted_9500-series_CPUs_confirmed_to_be_Poulson_Itaniums.html| url-status = live}}</ref> Intel later posted Itanium 9500 reference manual.<ref>{{cite web| url = http://www.cpu-world.com/news_2012/2012071101_Intel_publishes_Itanium_9500_reference_manual.html| title = Intel publishes Itanium 9500 reference manual| access-date = 2012-08-02| archive-date = 2017-10-08| archive-url = https://web.archive.org/web/20171008075849/http://www.cpu-world.com/news_2012/2012071101_Intel_publishes_Itanium_9500_reference_manual.html| url-status = live}}</ref> The models are the following:<ref name="cpu-world.com"/><ref>{{cite web|title=Products formerly Poulson|url=http://ark.intel.com/products/codename/26643/Poulson|website=Intel® ARK (Product Specs)|access-date=May 31, 2017|archive-date=May 18, 2017|archive-url=https://web.archive.org/web/20170518065154/http://ark.intel.com/products/codename/26643/Poulson|url-status=live}}</ref> :{| class="wikitable" |- !Processor number||Frequency||Cache |- |9520||1.73 GHz||20MB |- |9540||2.13 GHz||24MB |- |9550||2.40 GHz||32MB |- |9560||2.53 GHz||32MB |}
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