Editing MOS Technology 6502 (section)

===Registers===
Like its precursor, the 6800, the 6502 has very few [[processor register|registers]]. They include<ref>{{Cite book |title=MOS MICROCOMPUTERS PROGRAMMING MANUAL |date=January 1976 |publisher=MOS TECHNOLOGY, INC. |chapter=PROGRAMMING MODEL MCS650X}}</ref>

* <code>A</code> = 8-bit [[accumulator (computing)|accumulator]] register
* <code>P</code> = 7-bit<ref>{{cite book |last=Anderson |first=J.S. |date=2012-08-21 |title=Microprocessor Technology |url=https://books.google.com/books?id=VKjkUsCV4moC&pg=PA153 |publisher=[[Routledge]] |page=153 |isbn=9781136078057}}</ref> processor [[status register]]
** <code>n</code> = [[Negative flag|Negative]]
** <code>v</code> = [[Overflow flag|Overflow]]
** <code>b</code> = Break (only in stack values, not in hardware<ref>{{Cite web |title=Status flags |url=https://www.nesdev.org/wiki/Status_flags |access-date=2024-06-11 |website=NESdev Wiki |language=en}}</ref>)
** <code>d</code> = [[Binary-coded decimal|Decimal]]
** <code>i</code> = [[Interrupt]] disable
** <code>z</code> = [[Zero flag|Zero]]
** <code>c</code> = [[Carry flag|Carry]]
* <code>PC</code> = 16-bit [[program counter]]
* <code>S</code> = 8-bit [[stack (abstract data type)|stack pointer]]
* <code>X</code> = 8-bit [[index register]]
* <code>Y</code> = 8-bit index register

This compares to a contemporaneous competitor, the [[Intel 8080]], which likewise has one 8-bit accumulator and a 16-bit program counter, but has six more general-purpose 8-bit registers (which can be combined into three 16-bit pointers) and a larger 16-bit stack pointer.<ref>{{cite web |title=8080A/8080A-1/8080A-2 8-Bit N Channel Microprocessor |url=http://www.elektronikjk.com/technika_komputerowa/CPU/Intel_8080A.pdf |publisher=Intel |access-date=November 16, 2021 |archive-date=November 15, 2021 |archive-url=https://web.archive.org/web/20211115165927/http://www.elektronikjk.com/technika_komputerowa/CPU/Intel_8080A.pdf |url-status=live }}</ref>

In order to make up somewhat for the lack of registers, the 6502 includes a ''[[zero page]]'' addressing mode that uses one address byte in the instruction instead of the two needed to address the full {{val|64|u=KB}} of memory. This provides fast access to the first {{val|256|u=bytes}} of RAM by using shorter instructions. For instance, an instruction to add a value from memory to the value in the accumulator would normally be three bytes, one for the instruction and two for the 16-bit address. Using the zero page reduces this to an 8-bit address, reducing the total instruction length to two bytes, and thus improving instruction performance.

The stack address space is [[Wiktionary:Hardwired|hardwired]] to memory page <code>$01</code>, i.e. the address range <code>$0100</code>–<code>$01FF</code> (<code>256</code>–<code>511</code>). Software access to the stack is done via four implied addressing mode instructions, whose functions are to push or pop (pull) the accumulator or the processor status register. The same stack is also used for subroutine calls via the JSR (jump to subroutine) and RTS (return from subroutine) instructions and for [[interrupt]] handling.