Editing PIC microcontrollers (section)

====PIC32MX====
In November 2007, Microchip introduced the [https://ww1.microchip.com/downloads/en/DeviceDoc/61177a.pdf PIC32MX] family of 32-bit microcontrollers, based on the [[MIPS instruction set|MIPS32 M4K Core]].<ref>{{cite web |url=http://www.mips.com/products/processors/32-64-bit-cores/mips32-m4k/ |title=MIPS32® M4K® Core - MIPS Technologies -MIPS Everywhere - MIPS Technologies |access-date=2009-01-21 |url-status=dead |archive-url=https://web.archive.org/web/20090202094206/http://mips.com/products/processors/32%2D64%2Dbit%2Dcores/mips32%2Dm4k/ |archive-date=2009-02-02 }}</ref> The device can be programmed using the [https://archive.today/20130128153047/http://microchip.com/c32 Microchip MPLAB C Compiler for PIC32 MCUs], a variant of the GCC compiler. The first 18 models currently in production (PIC32MX3xx and PIC32MX4xx) are pin to pin compatible and share the same peripherals set with the PIC24FxxGA0xx family of (16-bit) devices, allowing the use of common libraries, software and hardware tools. Today, starting at 28 pin in small QFN packages up to high performance devices with Ethernet, CAN and USB OTG, full family range of mid-range 32-bit microcontrollers are available.

The PIC32 architecture brought a number of new features to Microchip portfolio, including:

* The highest execution speed 80&nbsp;MIPS (120+<ref>{{cite web |title=32-bit PIC MCUs |url=http://www.microchip.com/en_US/family/pic32/ |access-date=13 October 2010}}</ref> [[Dhrystone]] {{nowrap|MIPS @ 80 MHz}})
* The largest flash memory: 512&nbsp;kB
* One instruction per clock cycle execution
* The first cached processor
* Allows execution from RAM
* Full Speed Host/Dual Role and OTG USB capabilities
* Full [[JTAG]] and 2-wire programming and debugging
* Real-time trace