Editing Peripheral Component Interconnect (section)

==PCI bus transactions==
PCI bus traffic consists of a series of PCI bus transactions.  Each transaction consists of an ''address phase'' followed by one or more ''data phases''.  The direction of the data phases may be from initiator to target (write transaction) or vice versa (read transaction), but all of the data phases must be in the same direction.  Either party may pause or halt the data phases at any point.  (One common example is a low-performance PCI device that does not support [[Burst mode (computing)|burst transactions]], and always halts a transaction after the first data phase.)

Any PCI device may initiate a transaction.  First, it must request permission from a PCI bus arbiter on the motherboard.  The arbiter grants permission to one of the requesting devices.  The initiator begins the address phase by broadcasting a 32-bit address plus a [[4-bit computing|4-bit]] command code, then waits for a target to respond.  All other devices examine this address and one of them responds a few cycles later.

64-bit addressing is done using a two-stage address phase.  The initiator broadcasts the low 32 address bits, accompanied by a special "dual address cycle" command code.  Devices that do not support 64-bit addressing can simply not respond to that command code.  The next cycle, the initiator transmits the high 32 address bits, plus the real command code.  The transaction operates identically from that point on.  To ensure compatibility with 32-bit PCI devices, it is forbidden to use a dual address cycle if not necessary, i.e. if the high-order address bits are all zero.

While the PCI bus transfers 32 bits per data phase, the initiator transmits 4 active-low byte enable signals indicating which [[8-bit computing|8-bit]] bytes are to be considered significant.  In particular, a write must affect only the enabled bytes in the target PCI device.  They are of little importance for memory reads, but I/O reads might have side effects.  The PCI standard explicitly allows a data phase with no bytes enabled, which must behave as a no-op.

===PCI address spaces===
PCI has three address spaces: memory, I/O address, and configuration.

Memory addresses are 32&nbsp;bits (optionally 64 bits) in size, support [[cache (computing)|caching]] and can be burst transactions.

I/O addresses are for compatibility with the Intel [[x86 architecture]]'s I/O port address space. Although the PCI bus specification allows burst transactions in any address space, most devices only support it for memory addresses and not I/O.

Finally, [[PCI configuration space]] provides access to 256 bytes of special configuration registers per PCI device.  Each PCI slot gets its own configuration space address range. The registers are used to configure devices memory and I/O address ranges they should respond to from transaction initiators.  When a computer is first turned on, all PCI devices respond only to their configuration space accesses. The computer's BIOS scans for devices and assigns Memory and I/O address ranges to them.

If an address is not claimed by any device, the transaction initiator's address phase will time out causing the initiator to abort the operation.  In case of reads, it is customary to supply all-ones for the read data value (0xFFFFFFFF) in this case. PCI devices therefore generally attempt to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.

===PCI command codes===
{{See also|PCI configuration space}}
There are 16 possible 4-bit command codes, and 12 of them are assigned. With the exception of the unique dual address cycle, the least significant bit of the command code indicates whether the following data phases are a read (data sent from target to initiator) or a write (data sent from an initiator to target). PCI targets must examine the command code as well as the address and not respond to address phases that specify an unsupported command code.

The commands that refer to cache lines depend on the [[PCI configuration space]] cache line size register being set up properly; they may not be used until that has been done.

; 0000{{colon}} Interrupt Acknowledge
: This is a special form of read cycle implicitly addressed to the interrupt controller, which returns an interrupt vector. The 32-bit address field is ignored. One possible implementation is to generate an interrupt acknowledge cycle on an ISA bus using a PCI/ISA bus bridge. This command is for [[IBM PC compatible|IBM PC compatibility]]; if there is no [[Intel 8259]] style interrupt controller on the PCI bus, this cycle need never be used.

; 0001{{colon}} Special Cycle
: This cycle is a special broadcast write of system events that PCI card may be interested in. The address field of a special cycle is ignored, but it is followed by a data phase containing a payload message. The currently defined messages announce that the processor is stopping for some reason (e.g. to save power). No device ever responds to this cycle; it is always terminated with a master abort after leaving the data on the bus for at least 4 cycles.

; 0010{{colon}} I/O Read
: This performs a read from I/O space. All 32 bits of the read address are provided, so that a device may (for compatibility reasons) implement less than 4 bytes worth of I/O registers. If the byte enables request data not within the address range supported by the PCI device (e.g. a 4-byte read from a device which only supports 2 bytes of I/O address space), it must be terminated with a target abort. Multiple data cycles are permitted, using linear (simple incrementing) burst ordering.
: The PCI standard is discouraging the use of I/O space in new devices, preferring that as much as possible be done through main memory mapping.

; 0011{{colon}} I/O Write
: This performs a write to I/O space.

; 010''x''{{colon}} Reserved
: A PCI device must not respond to an address cycle with these command codes.

; 0110{{colon}} Memory Read
: This performs a read cycle from memory space.  Because the smallest memory space a PCI device is permitted to implement is 16 bytes,<ref name="pci23"/><ref name="pci30"/>{{rp|§6.5.2.1}} the two least significant bits of the address are not needed during the address phase; equivalent information will arrive during the data phases in the form of byte select signals.  They instead specify the order in which burst data must be returned.<ref name="pci23"/><ref name="pci30"/>{{rp|§3.2.2.2}}  If a device does not support the requested order, it must provide the first word and then disconnect.
: If a memory space is marked as "prefetchable", then the target device must ignore the byte-select signals on a memory read and always return 32 valid bits.

; 0111{{colon}} Memory Write
: This operates similarly to a memory read.  The byte select signals are more important in a write, as unselected bytes must not be written to memory.
: Generally, PCI writes are faster than PCI reads, because a device may buffer the incoming write data and release the bus faster.  For a read, it must delay the data phase until the data has been fetched.

; 100''x''{{colon}} Reserved
: A PCI device must not respond to an address cycle with these command codes.

; 1010{{colon}} Configuration Read
: This is similar to an I/O read, but reads from PCI configuration space.  A device must respond only if the low 11 bits of the address specify a function and register that it implements, and if the special IDSEL signal is asserted.  It must ignore the high 21 bits. Burst reads (using linear incrementing) are permitted in PCI configuration space.
: Unlike I/O space, standard PCI configuration registers are defined so that reads never disturb the state of the device.  It is possible for a device to have configuration space registers beyond the standard 64 bytes which have read side effects, but this is rare.<ref>{{Cite mailing list |url=http://marc.info/?l=linux-kernel&m=100698181808532 |title=Re: sym53c875: reading /proc causes SCSI parity error |first=Gérard |last=Roudier |date=2001-11-28 |mailing-list=linux-kernel}}</ref>
: Configuration space accesses often have a few cycles of delay to allow the IDSEL lines to stabilize, which makes them slower than other forms of access. Also, a configuration space access requires a multi-step operation rather than a single machine instruction. Thus, it is best to avoid them during routine operation of a PCI device.

; 1011{{colon}} Configuration Write
: This operates analogously to a configuration read.

; 1100{{colon}} Memory Read Multiple
: This command is identical to a generic memory read, but includes the hint that a long read burst will continue beyond the end of the current cache line, and the target should internally [[prefetch buffer|prefetch]] a large amount of data.  A target is always permitted to consider this a synonym for a generic memory read.

; 1101{{colon}} Dual Address Cycle
: When accessing a memory address that requires more than 32 bits to represent, the address phase begins with this command and the low 32 bits of the address, followed by a second cycle with the actual command and the high 32 bits of the address.  PCI targets that do not support 64-bit addressing may simply treat this as another reserved command code and not respond to it.  This command code may only be used with a non-zero high-order address word; it is forbidden to use this cycle if not necessary.

; 1110{{colon}} Memory Read Line
: This command is identical to a generic memory read, but includes the hint that the read will continue to the end of the cache line.  A target is always permitted to consider this a synonym for a generic memory read.

; 1111{{colon}} Memory Write and Invalidate
: This command is identical to a generic memory write, but comes with the guarantee that one or more whole cache lines will be written, with all byte selects enabled.  This is an optimization for write-back caches snooping the bus.  Normally, a write-back cache holding dirty data must interrupt the write operation long enough to write its own dirty data first.  If the write is performed using this command, the data to be written back is guaranteed to be irrelevant, and may simply be invalidated in the write-back cache.
: This optimization only affects the snooping cache, and makes no difference to the target, which may treat this as a synonym for the memory write command.