Editing Random-access machine (section)

=== The indirect COPY instruction ===
Probably the most useful of the added instructions is COPY. Indeed, Elgot-Robinson (1964) provide their models P<sub>0</sub> and P'<sub>0</sub> with the COPY instructions, and Cook-Reckhow (1973) provide their accumulator-based model with only two indirect instructions{{spaced ndash}}COPY to accumulator indirectly, COPY from accumulator indirectly.

'''A plethora of instructions''': Because any instruction acting on a single register can be augmented with its indirect "dual" (including conditional and unconditional jumps, cf the Elgot-Robinson model), the inclusion of indirect instructions will double the number of single parameter/register instructions (e.g. INC (d, r), INC (i, r)). Worse, every two parameter/register instruction will have 4 possible varieties, e.g.:

: CPY (d, r<sub>s</sub>, d, r<sub>d</sub> ) = COPY directly from source-register directly to destination-register
: CPY (i, r<sub>sp</sub>, d, r<sub>d</sub> ) = COPY to destination-register indirectly using the source address to be found in the source-pointer register r<sub>sp</sub>.
: CPY (d, r<sub>s</sub>, i, r<sub>dp</sub> ) = COPY contents of source-register indirectly into register using destination address to be found in the destination-pointer register r<sub>dp</sub>.
: CPY (i, r<sub>sp</sub>, i, r<sub>dp</sub> ) = COPY indirectly the contents of the source register with address to be found in source-pointer register r<sub>sp</sub>, into the destination register with address to be found in the destination-pointer register r<sub>dp</sub>)

In a similar manner every three-register instruction that involves two source registers r<sub>s1</sub> r<sub>s2</sub> and a destination register r<sub>d</sub> will result in 8 varieties, for example the addition:
:: [r<sub>s1</sub>] + [r<sub>s2</sub>] → r<sub>d</sub>

will yield:
* ADD ( d, r<sub>s1</sub>, d, r<sub>s2</sub>, d, r<sub>d</sub> )
* ADD ( i, r<sub>sp1</sub>, d, r<sub>s2</sub>, d, r<sub>d</sub> )
* ADD ( d, r<sub>s1</sub>, i, r<sub>sp2</sub>, d, r<sub>d</sub> )
* ADD ( i, r<sub>sp1</sub>, i, r<sub>sp2</sub>, d, r<sub>d</sub> )
* ADD ( d, r<sub>s1</sub>, d, r<sub>s2</sub>, i, r<sub>dp</sub> )
* ADD ( i, r<sub>sp1</sub>, d, r<sub>s2</sub>, i, r<sub>dp</sub> )
* ADD ( d, r<sub>s1</sub>, i, r<sub>sp2</sub>, i, r<sub>dp</sub> )
* ADD ( i, r<sub>sp1</sub>, i, r<sub>sp2</sub>, i, r<sub>dp</sub> )

If we designate one register to be the "accumulator" (see below) and place strong restrictions on the various instructions allowed then we can greatly reduce the plethora of direct and indirect operations. However, one must be sure that the resulting reduced instruction-set is sufficient, and we must be aware that the reduction will come at the expense of more instructions per "significant" operation.