Editing Silicon Integrated Systems (section)

=== Discrete 3D Graphics chips ===
{| class="wikitable"
|-
! rowspan="2" |Model
! rowspan="2" |Launch
! rowspan="2" |[[Semiconductor device fabrication|Fab]] ([[Nanometer|nm]])
! rowspan="2" |[[Computer bus|Bus]] [[I/O interface|interface]]
! rowspan="2" |Core clock ([[Hertz|MHz]])
! rowspan="2" |Memory clock ([[Hertz|MHz]])
! rowspan="2" |Core config<sup>1</sup>
! colspan="4" |[[Fillrate]]
! colspan="4" |Memory
! colspan="2" |[[Application programming interface|API]] support
|-
!MOperations/s
!MPixels/s
!MTexels/s
!MVertices/s
!Size ([[Megabyte|MB]])
!Bandwidth ([[Gigabyte|GB]]/s)
!Bus type
!Bus width ([[bit]])
![[Direct3D]]
![[OpenGL]]
|-
!SiS 6326
|1997
|
|AGP 1×
PCI
|40
|45-80
45–90

66–133
| rowspan="3" |1:0:1:1
|40
|40
|40
|0
|2-8
|0.36-0.64
0.36-0.72

0.53-1.06
|FPM
EDO

SDR
|64
|5.0
|N/A
|-
!SiS 300
|2000
|250&nbsp;nm
|AGP 4×
PCI
|125
|166
|125
|125
|125
|0
|64
|2.66
|SDR
|128
|6.0
|1.1
|-
!SiS 305
|2000
|250&nbsp;nm
|AGP 4×
PCI
|125
|125
|125
|125
|125
|0
|32
|1.00
|SDR
|64
|6.0
|1.1
|-
!SiS 315
|2001
|
|AGP 4×
PCI
|166
|166
333
|2:0:4:2
|333
|333
|667
|0
|64
|2.66
5.33
|SDR
DDR
|128
|7.0
|1.3
|-
!SiS 315E
|2001
|
|AGP 4×
PCI
|143
|143
286
|2:0:2:2
|286
|286
|286
|0
|32
|1.14
2.28
|SDR
DDR
|64
|7.0
|1.3
|-
!Xabre 80
|2002
|150&nbsp;nm
|AGP 4×
|200
|333
|4:1:8:4
|800
|800
|1600
|50
|64
|5.33
|DDR
|128
|8.1
|1.3
|-
!Xabre 200
|2002
|150&nbsp;nm
|AGP 8×
|200
|400
|4:1:8:4
|800
|800
|1600
|50
|32
64
|6.40
|DDR
|128
|8.1
|1.3
|-
!Xabre 400
|2002
|150&nbsp;nm
|AGP 8×
|250
|400
|4:1:8:4
|1000
|1000
|2000
|67.5
|64
128
|8.00
|DDR
|128
|8.1
|1.3
|-
!Xabre 600
|2002
|130&nbsp;nm
|AGP 8×
|300
|600
|4:1:8:4
|1200
|1200
|2400
|75
|64
128
|9.60
|DDR
|128
|8.1
|1.3
|}