Editing Single-photon avalanche diode (section)

===Optical fill factor===
For a single SPAD, the ratio of its optically sensitive area, A<sub>act</sub>, to its total area, A<sub>tot</sub>, is called the [[Fill factor (image sensor)|fill factor]], {{Nowrap|FF {{=}} (A<sub>act</sub> / A<sub>tot</sub>) × 100%}}. As SPADs require a guard ring <ref name="Cova96" /><ref name=":1" /> to prevent premature edge breakdown, the optical fill factor becomes a product of the diode shape and size with relation its guard ring. If the active area is large and the outer guard ring is thin, the device will have a high fill factor. With a single device, the most efficient method to ensure full utilisation of the area and maximum sensitivity is to focus the incoming optical signal to be within the device's active area, i.e. all incident photons are absorbed within the planar area of the p-n junction such that any photon within this area can trigger an avalanche.

[[Fill factor (image sensor)|Fill factor]] is more applicable when we consider arrays of SPAD devices.<ref name=":5">{{Cite journal|last=Claudio Bruschini, Harald Homulle, Ivan Michel Antolovic, Samuel Burri & Edoardo Charbon|date=2019|title=Single-photon avalanche diode imagers in biophotonics: review and outlook|url=https://www.nature.com/articles/s41377-019-0191-5|journal=Light: Science & Applications|volume=8}}</ref><ref>{{Cite journal |url=https://opg.optica.org/optica/viewmedia.cfm?uri=optica-10-9-1124&html=true |access-date=2023-08-29 |journal=Optica |doi=10.1364/optica.488853 | title=Single-photon detection for long-range imaging and sensing | date=2023 | last1=Hadfield | first1=Robert H. | last2=Leach | first2=Jonathan | last3=Fleming | first3=Fiona | last4=Paul | first4=Douglas J. | last5=Tan | first5=Chee Hing | last6=Ng | first6=Jo Shien | last7=Henderson | first7=Robert K. | last8=Buller | first8=Gerald S. | volume=10 | issue=9 | page=1124 | s2cid=259687483 | doi-access=free |bibcode=2023Optic..10.1124H | hdl=20.500.11820/4d60bb02-3c2c-4f86-a737-f985cb8613d8 | hdl-access=free }}</ref> Here the diode active area may be small or commensurate with the guard ring's area. Likewise, the fabrication process of the SPAD array may put constraints on the separation of one guard ring to another, i.e. the minimum separation of SPADs. This leads to the situation where the area of the array becomes dominated by guard ring and separation regions rather than optically receptive p-n junctions. The fill factor is made worse when circuitry must be included within the array as this adds further separation between optically receptive regions. One method to mitigate this issue is to increase the active area of each SPAD in the array such that guard rings and separation are no longer dominant, however for CMOS integrated SPADs the erroneous detections caused by dark counts increases as the diode size increases.<ref>{{Cite journal|last=D. Bronzi, F. Villa, S. Bellisai, S. Tisa, G. Ripamonti, and A. Tosi|s2cid=120426318|editor2-first=Jaromír|editor2-last=Fiurásek|editor1-first=Roman|editor1-last=Sobolewski|date=2013|title=Figures of Merit for CMOS SPADs and Arrays|journal=Proc. SPIE 8773, Photon Counting Applications IV; and Quantum Optics and Quantum Information Transfer and Processing|series=Photon Counting Applications IV; and Quantum Optics and Quantum Information Transfer and Processing|volume=8773|page=877304|doi=10.1117/12.2017357|bibcode=2013SPIE.8773E..04B}}</ref>

==== Geometric improvements ====
One of the first methods to increase fill factors in arrays of circular SPADs was to offset the alignment of alternate rows such that the curve of one SPAD partially uses the area between the two SPADs on an adjacent row.<ref>{{Cite book|last=R. J. Walker, E. A. G. Webster, J. Li, N. Massari and R. K. Henderson|title=2012 IEEE Nuclear Science Symposium and Medical Imaging Conference Record (NSS/MIC) |chapter=High fill factor digital Silicon Photomultiplier structures in 130nm CMOS imaging technology |s2cid=26430979|date=2012|pages=1945–1948|doi=10.1109/NSSMIC.2012.6551449|isbn=978-1-4673-2030-6}}</ref> This was effective but complicated the routing and layout of the array.

To address fill factor limitations within SPAD arrays formed of circular SPADs, other shapes are utilised as these are known to have higher maximum area values within a typically square pixel area and have higher packing ratios. A square SPAD within a square pixel achieves the highest fill factor, however the sharp corners of this geometry are known to cause premature breakdown of the device, despite a guard ring and consequently produce SPADs with high dark count rates. To compromise, square SPADs with sufficiently rounded corners have been fabricated.<ref>{{Cite journal|last=J. A. Richardson, E. A. G. Webster, L. A. Grant and R. K. Henderson|s2cid=35369946|date=2011|title=Scaleable Single-Photon Avalanche Diode Structures in Nanometer CMOS Technology|journal=IEEE Transactions on Electron Devices|volume=58|issue=7|pages=2028–2035|doi=10.1109/TED.2011.2141138|bibcode=2011ITED...58.2028R}}</ref> These are termed [[Fermat curve|Fermat]] shaped SPADs while the shape itself is a [[Superellipse|super-ellipse]] or a Lamé curve. This nomenclature is common in the SPAD literature, however the Fermat curve refers to a special case of the super-ellipse that puts restrictions on the ratio of the shape's length, "a" and width, "b" (they must be the same, a = b = 1) and restricts the degree of the curve "n" to be even integers (2, 4, 6, 8 etc). The degree "n" controls the curvature of the shape's corners. Ideally, to optimise the shape of the diode for both low noise and a high fill factor, the shape's parameters should be free of these restrictions.

To minimise the spacing between SPAD active areas, researchers have removed all active circuitry from the arrays<ref name=":2">{{Cite journal|last=Richard Walker and Leo H. C. Braga and Ahmet T. Erdogan and Leonardo Gasparini and Lindsay A. Grant and Robert Henderson and Nicola Massari and Matteo Perenzoni and David Stoppa|date=2013|title=A 92k SPAD Time-Resolved Sensor in 0.13μm CIS Technology for PET/MRI Applications|url=https://www.imagesensors.org/Past%20Workshops/2013%20Workshop/2013%20Papers/06-5_085-Walker-paper.pdf|journal=In Proc: International Image Sensor Workshop (IISW), 2013}}</ref> and have also explored the use of NMOS only CMOS SPAD arrays to remove SPAD guard ring to PMOS n-well spacing rules.<ref>{{Cite book|last=E. Webster, R. Walker, R. Henderson, and L. Grant|title=2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC) |chapter=A silicon photomultiplier with &gt;30% detection efficiency from 450&ndash;750nm and 11.6μm pitch NMOS-only pixel with 21.6% fill factor in 130nm CMOS |s2cid=10130988|date=2012|pages=238–241|doi=10.1109/ESSDERC.2012.6343377|isbn=978-1-4673-1708-5}}</ref> This is of benefit but is limited by routing distances and congestion into the centre SPADs for larger arrays. The concept has been extended to develop arrays that use clusters of SPADs in so-called mini-SiPM arrangements<ref name=":2" /> whereby a smaller array is provided with its active circuitry at one edge, allowing a second small array to be abutted on a different edge. This reduced the routing difficulties by keeping the number of diodes in the cluster manageable and creating the required number of SPADs in total from collections of those clusters.

A significant jump in fill factor and array pixel pitch was achieved by sharing the deep n-well of the SPADs in CMOS processes,<ref>{{Cite book|last=L. Pancheri and D. Stoppa|title=ESSDERC 2007 - 37th European Solid State Device Research Conference |chapter=Low-Noise CMOS single-photon avalanche diodes with 32 ns dead time |s2cid=32255573|date=2007|pages=362–365|doi=10.1109/ESSDERC.2007.4430953|isbn=978-1-4244-1123-8}}</ref><ref name=":2" /> and more recently also sharing portions of the guard-ring structure.<ref name=":3">{{Cite journal|last=K Morimoto and E Charbon|date=2020|title=High fill-factor miniaturized SPAD arrays with a guard-ring-sharing technique|url=https://www.osapublishing.org/oe/abstract.cfm?uri=oe-28-9-13068|journal=Optics Express|volume=28|issue=9|pages=13068–13080|doi=10.1364/OE.389216|pmid=32403788|bibcode=2020OExpr..2813068M|via=OSA|doi-access=free}}</ref> This removed one of the major guard-ring to guard-ring separation rules and allowed the fill-factor to increase towards 60<ref>{{Cite journal|last=Ximing Ren, Peter W. R. Connolly, Abderrahim Halimi, Yoann Altmann, Stephen McLaughlin, Istvan Gyongy, Robert K. Henderson, and Gerald S. Buller|date=2018|title=High-resolution depth profiling using a range-gated CMOS SPAD quanta image sensor|url=https://www.osapublishing.org/oe/abstract.cfm?uri=oe-26-5-5541|journal=Optics Express|volume=26|issue=5|pages=5541–5557|doi=10.1364/OE.26.005541|pmid=29529757|bibcode=2018OExpr..26.5541R|doi-access=free|hdl=20.500.11820/16e2045b-7416-4ca6-9435-655b84af59a5|hdl-access=free}}</ref> or 70%.<ref>{{Cite journal|last=E. Vilella, O. Alonso, A. Montiel, A. Vila, and A. Dieguez|date=2013|title=A Low-Noise Time-Gated Single-Photon Detector in a HV-CMOS Technology for Triggered Imaging|journal=Sensors and Actuators A: Physical|volume=201|pages=342–351|doi=10.1016/j.sna.2013.08.006|bibcode=2013SeAcA.201..342V }}</ref><ref>{{Cite book|s2cid=6436431|date=2011|pages=107–110|doi=10.1109/ESSCIRC.2011.6044926 |chapter=A 100m-range 10-frame/S 340×96-pixel time-of-flight depth sensor in 0.18μm CMOS |title=2011 Proceedings of the ESSCIRC (ESSCIRC) |last1=Niclass |first1=Cristiano |last2=Soga |first2=Mineki |last3=Matsubara |first3=Hiroyuki |last4=Kato |first4=Satoru |isbn=978-1-4577-0703-2 }}</ref> The n-well and guard ring sharing idea has been crucial in efforts towards lowering pixel pitch and increasing the total number of diodes in the array. Recently SPAD pitches have been reduced to 3.0&nbsp;um<ref>{{Cite journal|last=Ziyang You, Luca Parmesan, Sara Pellegrini and Robert K. Henderson|date=2017|title=3um Pitch, 1um Active Diameter SPAD Arrays in 130nm CMOS Imaging Technology|url=https://www.imagesensors.org/Past%20Workshops/2017%20Workshop/2017%20Papers/R21.pdf|journal=In Proc: International Image Sensor Workshop (IISW)}}</ref> and 2.2&nbsp;um.<ref name=":3" />

Porting a concept from photodiodes and APDs, researchers have also investigated the use of drift electric fields within the CMOS substrate to attract photo generated carriers towards a SPAD's active p-n junction.<ref>{{Cite journal|doi=10.3390/app10062155|title=Current-Assisted Single Photon Avalanche Diode (CASPAD) Fabricated in 350 nm Conventional CMOS|year=2020|last1=Jegannathan|first1=Gobinath|last2=Ingelberts|first2=Hans|last3=Kuijk|first3=Maarten|journal=Applied Sciences|volume=10|issue=6|page=2155|doi-access=free}}</ref> By doing so a large optical collection area can be achieved with a smaller SPAD region.

Another concept ported from CMOS image sensor technologies, is the exploration of stacked p-n junctions similar to [[Foveon X3 sensor|Foveon]] sensors. The idea being that higher-energy photons (blue) tend to be absorbed at a short absorption depth, i.e. near the silicon surface.<ref name=":4" /> Red and infra-red photons (lower energy) travel deeper into the silicon. If there is a junction at that depth, red and IR sensitivity can be improved.<ref>{{Cite journal|last=R. K. Henderson, E. A. G. Webster and L. A. Grant|s2cid=31895707|date=2013|title=A Dual-Junction Single-Photon Avalanche Diode in 130-nm CMOS Technology|journal=IEEE Electron Device Letters|volume=34|issue=3|pages=429–431|doi=10.1109/LED.2012.2236816|bibcode=2013IEDL...34..429H}}</ref><ref>{{Cite journal|last=H. Finkelstein, M. J. Hsu and S. C. Esener|date=2007|title=Dual-junction single-photon avalanche diode|url=https://ieeexplore.ieee.org/document/4375469|journal=Electronics Letters|volume=43|issue=22|page=1228|doi=10.1049/el:20072355|bibcode=2007ElL....43.1228F|via=IEEE|url-access=subscription}}{{dead link|date=July 2024|bot=medic}}{{cbignore|bot=medic}}</ref>

==== IC fabrication improvements ====
With the advancement of [[Three-dimensional integrated circuit|3D IC technologies]], i.e. stacking of integrated circuits, the fill factor could be enhanced further by allowing the top die to be optimised for a high fill-factor SPAD array, and the lower die for readout circuits and signal processing.<ref>{{Cite journal|s2cid=21729101|date=2018|title=High-Performance Back-Illuminated Three-Dimensional Stacked Single-Photon Avalanche Diode Implemented in 45-nm CMOS Technology|journal=IEEE Journal of Selected Topics in Quantum Electronics|volume=24|issue=6|page=2827669|doi=10.1109/JSTQE.2018.2827669|bibcode=2018IJSTQ..2427669L|url=http://infoscience.epfl.ch/record/256438/files/High-Performance%20Back-Illuminated%20Three-Dimensional%20Stacked%20Single-Photon%20Avalanche%20Diode%20Implemented%20in%2045-nm%20CMOS%20Technology.pdf|last1=Lee|first1=Myung-Jae|last2=Ximenes|first2=Augusto Ronchini|last3=Padmanabhan|first3=Preethi|last4=Wang|first4=Tzu-Jui|last5=Huang|first5=Kuo-Chin|last6=Yamashita|first6=Yuichiro|last7=Yaung|first7=Dun-Nian|last8=Charbon|first8=Edoardo|doi-access=free}}</ref> As small dimension, high-speed processes for transistors may require different optimisations than optically sensitive diodes, 3D-ICs allow the layers to be separately optimised.

==== Pixel-level optical improvements ====
As with CMOS image sensors [[Microlens|micro-lenses]] can be fabricated on the SPAD pixel array to focus light into the centre of the SPAD.<ref>{{Cite journal|last=G. Intermite and R. E. Warburton and A. McCarthy and X. Ren and F. Villa and A. J. Waddie and M. R. Taghizadeh and Y. Zou and Franco Zappa and Alberto Tosi and Gerald S. Buller|s2cid=91178727|editor3-first=Ralph B|editor3-last=James|editor2-first=Roman|editor2-last=Sobolewski|editor1-first=Ivan|editor1-last=Prochazka|date=2015|title=Enhancing the fill-factor of CMOS SPAD arrays using microlens integration|journal=SPIE: Photon Counting Applications 2015|series=Photon Counting Applications 2015|volume=9504|pages=64–75|doi=10.1117/12.2178950|bibcode=2015SPIE.9504E..0JI|hdl=11311/971983 |hdl-access=free}}</ref> As with a single SPAD, this allows light to only hit the sensitive regions and avoid both the guard ring and any routing that is needed within the array. This has also recently included Fresnel type lenses.<ref>{{Cite journal|last=Peter W. R. Connolly, Ximing Ren, Aongus McCarthy, Hanning Mai, Federica Villa, Andrew J. Waddie, Mohammad R. Taghizadeh, Alberto Tosi, Franco Zappa, Robert K. Henderson, and Gerald S. Buller|date=2020|title=High concentration factor diffractive microlenses integrated with CMOS single-photon avalanche diode detector arrays for fill-factor improvement|journal=Applied Optics|volume=59|issue=14|pages=4488–4498|doi=10.1364/AO.388993|pmid=32400429|pmc=7340373|bibcode=2020ApOpt..59.4488C|doi-access=free}}</ref>

==== Pixel pitch ====
The above fill-factor enhancement methods, mostly concentrating on SPAD geometry along with other advancements, have led SPAD arrays to recently push the 1 mega pixel barrier.<ref>{{Cite journal|last=Kazuhiro Morimoto, Andrei Ardelean, Ming-Lo Wu, Arin Can Ulku, Ivan Michel Antolovic, Claudio Bruschini, and Edoardo Charbon|date=2020|title=Megapixel time-gated SPAD image sensor for 2D and 3D imaging applications|url=https://www.osapublishing.org/optica/abstract.cfm?uri=optica-7-4-346|journal=Optica|volume=7|issue=4|pages=346–354|doi=10.1364/OPTICA.386574|arxiv=1912.12910|bibcode=2020Optic...7..346M|s2cid=209515304|via=OSA}}</ref> While this lags CMOS image sensors (with pitches now below 0.8&nbsp;um), this is a product of both the youth of the research field (with CMOS SPADs introduced in 2003) and the complications of high voltages, avalanche multiplication within the silicon and the required spacing rules.