Editing Step response (section)

====Control of settling time ====
The amplitude of ringing in the step response in Figure 3 is governed by the damping factor exp(−''ρt''). That is, if we specify some acceptable step response deviation from final value, say Δ, that is:

:<math> S(t)  \le 1 + \Delta, </math>

this condition is satisfied  regardless of the value of β ''A''<sub>OL</sub> provided the time is longer than the settling time, say ''t''<sub>S</sub>, given by:<ref>This estimate is a bit conservative (long) because the factor 1 /sin(φ) in the overshoot contribution  to ''S'' (''t'') has been replaced by  1 /sin(''φ'') ≈ 1.</ref>

:<math> \Delta = e^{- \rho t_S }\text{ or }t_S = \frac { \ln \frac{1}{\Delta} } { \rho } = \tau_2 \frac {2 \ln \frac{1} { \Delta}  } { 1 + \frac { \tau_2 } { \tau_1} } \approx 2 \tau_2 \ln \frac{1} { \Delta}, </math>

where the  τ<sub>1</sub>&nbsp;≫&nbsp;τ<sub>2</sub> is applicable because of  the overshoot control condition, which makes ''τ''<sub>1</sub>&nbsp;=&nbsp;''αβA''<sub>OL</sub> τ<sub>2</sub>. Often the settling time condition is referred to by saying the settling period is inversely proportional to the unity gain bandwidth,  because 1/(2''π''&nbsp;''τ''<sub>2</sub>) is close to this bandwidth for an amplifier with typical [[Frequency compensation#Dominant-pole compensation|dominant pole compensation]]. However, this result is more precise than this [[rule of thumb]]. As an example of this formula, if {{nowrap|1=Δ = 1/e<sup>4</sup> = 1.8 %,}} the settling time condition is  ''t''<sub>S</sub>&nbsp;=&nbsp;8&nbsp;''τ''<sub>2</sub>.

In general, control of overshoot sets the time constant ratio, and settling time ''t''<sub>S</sub> sets&nbsp;τ<sub>2</sub>.<ref name=Johns>{{cite book 
|author=David A. Johns & Martin K W
|title=Analog integrated circuit design
|year= 1997
|pages=234–235
|publisher=Wiley
|location=New York
|isbn=0-471-14448-7
|url=http://worldcat.org/isbn/0-471-14448-7}}</ref><ref name=Sansen>{{cite book 
|author=Willy M C Sansen
|title=Analog design essentials
|page=§0528 p. 163
|year= 2006
|publisher=Springer
|location=Dordrecht, The Netherlands
|isbn=0-387-25746-2
|url=http://worldcat.org/isbn/0-387-25746-2}}</ref><ref>According to Johns and Martin, ''op. cit.'', settling time is significant in [[switched capacitor|switched-capacitor circuits]], for example, where an op amp settling time must be less than half a clock period for sufficiently rapid charge transfer.</ref>