Editing X86 virtualization (section)

==== {{Anchor|Intel-VT-d|FLR}}I/O MMU virtualization (AMD-Vi and Intel VT-d) ====
{{See also|Input–output memory management unit#Virtualization}}
[[File:AMD-Vi boot log screenshot.png|upright=1.5|thumb|A [[Linux kernel]] log showing AMD-Vi information]]
An input/output memory management unit (IOMMU) allows guest [[virtual machine]]s to directly use [[peripheral]] devices, such as Ethernet, accelerated graphics cards, and hard-drive controllers, through [[direct memory access|DMA]] and [[interrupt]] remapping. This is sometimes called ''PCI passthrough''.<ref>{{cite web |title=Linux virtualization and PCI passthrough |url=http://www.ibm.com/developerworks/linux/library/l-pci-passthrough/ |publisher=IBM |access-date=10 November 2010 |url-status=dead |archive-url=https://web.archive.org/web/20091101161431/http://www.ibm.com/developerworks/linux/library/l-pci-passthrough/ |archive-date=1 November 2009}}</ref>

An IOMMU also allows operating systems to eliminate bounce buffers needed to allow themselves to communicate with peripheral devices whose memory address spaces are smaller than the operating system's memory address space, by using memory address translation. At the same time, an IOMMU also allows operating systems and hypervisors to prevent buggy or malicious hardware from [[DMA attack|compromising memory security]].
 
Both AMD and Intel have released their IOMMU specifications:
* AMD's I/O Virtualization Technology, "AMD-Vi", originally called "IOMMU"<ref>{{cite web |title=AMD I/O Virtualization Technology (IOMMU) Specification Revision 1.26 |url=http://support.amd.com/us/Processor_TechDocs/34434-IOMMU-Rev_1.26_2-11-09.pdf |access-date=2011-05-24 |url-status=live |archive-url=https://web.archive.org/web/20110124134140/http://support.amd.com/us/Processor_TechDocs/34434-IOMMU-Rev_1.26_2-11-09.pdf |archive-date=2011-01-24}}</ref>
* Intel's "Virtualization Technology for Directed I/O" (VT-d),<ref>{{cite web |url=http://www.intel.com/content/www/us/en/intelligent-systems/intel-technology/vt-directed-io-spec.html |title=Intel Virtualization Technology for Directed I/O (VT-d) Architecture Specification |access-date=2012-02-04 |url-status=dead |archive-url=https://web.archive.org/web/20130403045524/http://www.intel.com/content/www/us/en/intelligent-systems/intel-technology/vt-directed-io-spec.html |archive-date=2013-04-03}}</ref> included in most high-end (but not all) newer Intel processors since the Core 2 architecture.<ref>{{cite web |url=http://ark.intel.com/search/advanced?VTD=true |title=Intel Virtualization Technology for Directed I/O (VT-d) Supported CPU List |publisher=Ark.intel.com |access-date=2012-02-04 |url-status=dead |archive-url=http://archive.wikiwix.com/cache/20101027065321/http://ark.intel.com/search/advanced?VTD=true |archive-date=2010-10-27}}</ref>

In addition to the CPU support, both [[motherboard]] [[chipset]] and system firmware ([[BIOS]] or [[Unified Extensible Firmware Interface|UEFI]]) need to fully support the IOMMU I/O virtualization functionality for it to be usable. Only the [[Conventional PCI|PCI]] or [[PCI Express]] devices supporting ''function level reset'' (FLR) can be virtualized this way, as it is required for reassigning various [[PCI device function|device functions]] between virtual machines.<ref>{{Cite web
 |url         = http://www.pcisig.com/specifications/pciexpress/specifications/ECN_Function_Level_Reset_27jun2006.pdf
 |title       = PCI-SIG Engineering Change Notice: Function Level Reset (FLR)
 |date        = 2006-06-27
 |access-date  = 2014-01-10
 |website     = pcisig.com
 |url-status     = live
 |archive-url  = https://web.archive.org/web/20160304001637/http://pcisig.com/specifications/pciexpress/specifications/ECN_Function_Level_Reset_27jun2006.pdf
 |archive-date = 2016-03-04
}}</ref><ref>{{Cite web
 |url         = http://wiki.xen.org/wiki/VTd_HowTo
 |title       = Xen VT-d
 |date        = 2013-06-06
 |access-date  = 2014-01-10
 |website     = xen.org
 |url-status     = live
 |archive-url  = https://web.archive.org/web/20140209124212/http://wiki.xen.org/wiki/VTd_HowTo
 |archive-date = 2014-02-09
}}</ref>  If a device to be assigned does not support [[Message Signaled Interrupts]] (MSI), it must not share [[interrupt]] lines with other devices for the assignment to be possible.<ref>{{cite web
 |url         = http://www.linux-kvm.org/page/How_to_assign_devices_with_VT-d_in_KVM
 |title       = How to assign devices with VT-d in KVM
 |date        = 2014-04-23
 |access-date  = 2015-03-05
 |website     = linux-kvm.org
 |url-status     = live
 |archive-url  = https://web.archive.org/web/20150310220832/http://www.linux-kvm.org/page/How_to_assign_devices_with_VT-d_in_KVM
 |archive-date = 2015-03-10
}}</ref>
All [[conventional PCI]] devices routed behind a PCI/[[PCI-X]]-to-PCI Express bridge can be assigned to a guest virtual machine only all at once; PCI Express devices have no such restriction.