Editing 555 timer IC (section)

=== Bistable SR latch ===
{{stack|[[File:555 Bistabiel digitaal.svg|thumb|Schematic of a 555 in bistable [[SR latch]] mode]]}}{{stack|[[File:Inverted SR Flip-flop.svg|thumb|100px|[[Active-low]] [[SR latch]] symbol, but lacks /Q output]]}}<!-- NOTE: Need better version with /Q removed. user:sbmeirow -->

{{see also|Set-Reset latch}}

A 555 timer can act as an [[Active low|active-low]] [[Set-Reset latch|SR latch]] (though without an inverted {{overline|Q}} output) with two outputs: output pin is a [[Push–pull output|push-pull]] output, discharge pin is an [[open-collector]] output (requires a [[pull-up resistor]]).

For the schematic on the right, a {{overline|Reset}} input signal connects to the {{overline|RESET}} pin and connecting a {{overline|Set}} input signal to the {{overline|TR}} pin. Thus, pulling {{overline|Set}} momentarily low acts as a "set" and transitions the output to the high state (''V''<sub>CC</sub>). Conversely, pulling {{overline|Reset}} momentarily low acts as a "reset" and transitions the Out pin to the low state (GND).

No timing capacitors are required in a bistable configuration. The threshold input is grounded because it is unused.<ref>{{Cite book |last=Buiting |first=Jan |url=https://books.google.com/books?id=rZDbnQ0siCYC&q=555+pin+7+%22open+collector%22&pg=PA84 |title=308 Circuits |date=2003 |publisher=Elektor International Media |isbn=978-0-905705-66-8 |language=en}}</ref> The trigger and reset inputs may be held high via [[pull-up resistor]]s if they are normally [[Hi-Z]] and only enabled by connecting to ground.
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