Editing Digital signal processor (section)

==Modern DSPs==

Modern signal processors yield greater performance; this is due in part to both technological and architectural advancements like lower design rules, fast-access two-level cache, (E)[[Direct memory access|DMA]] circuitry, and a wider bus system. Not all DSPs provide the same speed and many kinds of signal processors exist, each one of them being better suited for a specific task, ranging in price from about US$1.50 to US$300.

[[Texas Instruments]] produces the [[TMS320C6000|C6000]] series DSPs, which have clock speeds of 1.2&nbsp;GHz and implement separate instruction and data caches. They also have an 8&nbsp;MiB 2nd level cache and 64 EDMA channels. The top models are capable of as many as 8000 MIPS ([[millions of instructions per second]]), use VLIW ([[very long instruction word]]), perform eight operations per clock-cycle and are compatible with a broad range of external peripherals and various buses (PCI/serial/etc). TMS320C6474 chips each have three such DSPs, and the newest generation C6000 chips support floating point as well as fixed point processing.

[[Freescale]] produces a multi-core DSP family, the MSC81xx. The MSC81xx is based on StarCore Architecture processors and the latest MSC8144 DSP combines four programmable SC3400 StarCore DSP cores. Each SC3400 StarCore DSP core has a clock speed of 1&nbsp;GHz.

[[XMOS]] produces a multi-core multi-threaded line of processor well suited to DSP operations, They come in various speeds ranging from 400 to 1600 MIPS. The processors have a multi-threaded architecture that allows up to 8 real-time threads per core, meaning that a 4 core device would support up to 32 real time threads. Threads communicate between each other with buffered channels that are capable of up to 80&nbsp;Mbit/s. The devices are easily programmable in C and aim at bridging the gap between conventional micro-controllers and FPGAs

[[CEVA, Inc.]] produces and licenses three distinct families of DSPs. Perhaps the best known and most widely deployed is the CEVA-TeakLite DSP family, a classic memory-based architecture, with 16-bit or 32-bit word-widths and single or dual [[Multiply–accumulate operation|MACs]]. The CEVA-X DSP family offers a combination of VLIW and SIMD architectures, with different members of the family offering dual or quad 16-bit MACs. The CEVA-XC DSP family targets [[Software-defined radio|Software-defined Radio (SDR)]] modem designs and leverages a unique combination of VLIW and Vector architectures with 32 16-bit MACs.

[[Analog Devices]] produce the [[Super Harvard Architecture Single-Chip Computer|SHARC]]-based DSP and range in performance from 66&nbsp;MHz/198 [[MFLOPS]] (million floating-point operations per second) to 400&nbsp;MHz/2400 MFLOPS. Some models support multiple [[binary multiplier|multiplier]]s and [[Arithmetic logic unit|ALU]]s, [[Single instruction, multiple data|SIMD]] instructions and audio processing-specific components and peripherals. The [[Blackfin]] family of embedded digital signal processors combine the features of a DSP with those of a general use processor. As a result, these processors can run simple [[operating system]]s like [[μCLinux]], velocity and [[Nucleus RTOS]] while operating on real-time data. The SHARC-based ADSP-210xx provides both [[delay slot|delayed branches]] and non-delayed branches.<ref>{{cite web |url=https://www.brown.edu/Departments/Engineering/Courses/En164/files/lab3_files/sharc_application_manual/chap1.pdf |title=Introduction of ADSP-21000 Family digital signal processors. |page=6 |accessdate=2023-12-01}}</ref>

[[NXP Semiconductors]] produce DSPs based on [[TriMedia (mediaprocessor)|TriMedia]] [[VLIW]] technology, optimized for audio and video processing. In some products the DSP core is hidden as a fixed-function block into a [[System-on-a-chip|SoC]], but NXP also provides a range of flexible single core media processors. The TriMedia media processors support both [[fixed-point arithmetic]] as well as [[floating-point arithmetic]], and have specific instructions to deal with complex filters and entropy coding.

[[CSR plc|CSR]] produces the Quatro family of SoCs that contain one or more custom Imaging DSPs optimized for processing document image data for scanner and copier applications.

[[Microchip Technology]] produces the PIC24 based dsPIC line of DSPs. Introduced in 2004, the dsPIC is designed for applications needing a true DSP as well as a true [[microcontroller]], such as motor control and in power supplies. The dsPIC runs at up to 40MIPS, and has support for 16 bit fixed point MAC, bit reverse and modulo addressing, as well as DMA.

Most DSPs use fixed-point arithmetic, because in real world signal processing the additional range provided by floating point is not needed, and there is a large speed benefit and cost benefit due to reduced hardware complexity. Floating point DSPs may be invaluable in applications where a wide dynamic range is required. Product developers might also use floating point DSPs to reduce the cost and complexity of software development in exchange for more expensive hardware, since it is generally easier to implement algorithms in floating point.

Generally, DSPs are dedicated integrated circuits; however DSP functionality can also be produced by using [[field-programmable gate array]] chips (FPGAs).

Embedded general-purpose RISC processors are becoming increasingly DSP like in functionality. For example, the [[Texas Instruments OMAP|OMAP3]] processors include an [[ARM Cortex-A8]] and C6000 DSP.

In Communications a new breed of DSPs offering the fusion of both DSP functions and H/W acceleration function is making its way into the mainstream. Such Modem processors include [[ASOCS]] ModemX and CEVA's XC4000.

In May 2018, Huarui-2 designed by Nanjing Research Institute of Electronics Technology of [[China Electronics Technology Group]] passed acceptance. With a processing speed of 0.4 TFLOPS, the chip can achieve better performance than current mainstream DSP chips.<ref>{{cite web|url=http://www.stdaily.com/index/kejixinwen/2018-06/15/content_681419.shtml|title=国产新型雷达芯片华睿2号与组网中心同时亮相-科技新闻-中国科技网首页|work=[[科技日报]]|access-date=2 July 2018}}</ref> The design team has begun to create Huarui-3, which has a processing speed in TFLOPS level and a support for [[artificial intelligence]].<ref name="xinhua">{{cite web|url=http://www.xinhuanet.com/fortune/2018-05/24/c_1122884014.htm|archive-url=https://web.archive.org/web/20180526123855/http://www.xinhuanet.com/fortune/2018-05/24/c_1122884014.htm|url-status=dead|archive-date=May 26, 2018|title=全国产芯片华睿２号通过"核高基"验收-新华网|author=王珏玢|work=[[Xinhua News Agency]]|access-date=2 July 2018|location=南京}}</ref>