Editing Interrupt (section)

==Processor response==
The processor samples the interrupt trigger signals or interrupt register during each instruction cycle, and will process the highest priority enabled interrupt found.
Regardless of the triggering method, the processor will begin interrupt processing at the next instruction boundary following a detected trigger, thus ensuring:
* The processor status{{efn|This might be just the [[Program counter|Program Counter (PC)]], a [[Program status word|PSW]] or multiple registers.}} is saved in a known manner. Typically the status is stored in a known location, but on some systems it is stored on a stack.
* All instructions before the one pointed to by the PC have fully executed.
* No instruction beyond the one pointed to by the PC has been executed, or any such instructions are undone before handling the interrupt.
* The execution state of the instruction pointed to by the PC is known.

There are several different architectures for handling interrupts. In some, there is a single interrupt handler<ref>{{cite book
 |       title = 3600 - Computer System - Reference Manual
 |          id = 60021300K
 |     version = Revision K
 |     chapter = Chapter IV - Interrupt System
 | chapter-url = http://bitsavers.org/pdf/cdc/3x00/48bit/3600/60021300K_3600_SysRef_Oct66.pdf#page=60
 |       pages = 4-1-4-12
 |        date = October 11, 1966
 |         url = http://bitsavers.org/pdf/cdc/3x00/48bit/3600/60021300K_3600_SysRef_Oct66.pdf
 |   publisher = [[Control Data Corporation]]
 | access-date = May 17, 2023
 }}
</ref> that must scan for the highest priority enabled interrupt. In others, there are separate interrupt handlers for separate interrupt types,<ref name="s360">{{cite book
 |     title = IBM System/360 Principles of Operation
 |        id = A22-6821-7
 |   edition = Eighth
 |      date = September 1968
 |      page = 77
 |       url = http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf
 | publisher = [[IBM]]
 }}
</ref> separate I/O channels or devices, or both.<ref>{{cite book
 | url         = http://bitsavers.org/pdf/dec/pdp11/handbooks/PDP-11_Handbook1979.pdf
 | title       = PDP-11 Processor Handbook PDP11/04/34a/44/60/70
 | chapter     = Chapter 5. PROGRAMMING TECHNIQUES
 | chapter-url = http://bitsavers.org/pdf/dec/pdp11/handbooks/PDP-11_Handbook1979.pdf#page=109
 | date        = 1979
 | pages       = [http://bitsavers.org/pdf/dec/pdp11/handbooks/PDP-11_Handbook1979.pdf#page=132 128–131]
 | access-date = March 1, 2025
 | publisher   = [[Digital Equipment Corporation]]
 }}
</ref><ref>{{cite book |url=http://bitsavers.org/pdf/dec/pdp11/handbooks/PDP11_PeripheralsHbk_1972.pdf |title=PDP-11 Peripherals and Interfacing Handbook |page=4 |publisher=[[Digital Equipment Corporation]]}}</ref>  Several interrupt causes may have the same interrupt type and thus the same interrupt handler, requiring the interrupt handler to determine the cause.<ref name="s360" />