Editing Memory paging (section)

===Ferranti Atlas===
The first computer to support paging was the supercomputer [[Atlas Computer (Manchester)|Atlas]],<ref>{{cite book
|last1 = Sumner
|first1 = F. H.
|last2 = Haley
|first2 = G.
|last3 = Chenh
|first3 = E. C. Y.
|title = Information Processing 1962
|series = IFIP Congress Proceedings
|chapter = The Central Control Unit of the 'Atlas' Computer
|volume = Proceedings of IFIP Congress 62
|year = 1962
| publisher = Spartan
}}</ref><ref>{{cite web
|url= http://www.computer50.org/kgill/atlas/atlas.html
|title= The Atlas
|publisher   = Department of Computer Science
|location    = University of Manchester
|url-status     = dead
|archive-url  = https://web.archive.org/web/20120728105352/http://www.computer50.org/kgill/atlas/atlas.html
|archive-date = 2012-07-28
}}</ref><ref>{{cite web
|url         = http://www.chilton-computing.org.uk/acl/technology/atlas/p005.htm
|title       = Atlas Architecture
|work        = Atlas Computer
|publisher   = Atlas Computer Laboratory
|location    = Chilton
|url-status     = live
|archive-url  = https://web.archive.org/web/20121210142240/http://www.chilton-computing.org.uk/acl/technology/atlas/p005.htm
|archive-date = 2012-12-10
}}</ref> jointly developed by [[Ferranti]], the [[University of Manchester]] and [[Plessey]] in 1963. The machine had an associative ([[Content-addressable memory|content-addressable]]) memory with one entry for each 512 word page. The Supervisor<ref>{{cite book
|last1       = Kilburn
|first1      = T.
|last2       = Payne
|first2      = R. B.
|last3       = Howarth
|first3      = D. J.
|title       = Computers - Key to Total Systems Control
|series      = Conferences Proceedings
|pages       = 279–294
|chapter     = The Atlas Supervisor
|chapter-url  = http://www.chilton-computing.org.uk/acl/technology/atlas/p019.htm
|volume      = 20, Proceedings of the Eastern Joint Computer Conference Washington, D.C.
|date        = December 1961
|publisher   = Macmillan
|url-status     = live
|archive-url  = https://web.archive.org/web/20091231062425/http://www.chilton-computing.org.uk/acl/technology/atlas/p019.htm
|archive-date = 2009-12-31
}}
</ref> handled non-equivalence interruptions{{efn|A non-equivalence interruption occurs when the high order bits of an address do not match any entry in the associative memory.}} and managed the transfer of pages between core and drum in order to provide a one-level store<ref>{{cite journal
|last1       = Kilburn
|first1      = T.
|last2       = Edwards
|first2      = D. B. G.
|last3       = Lanigan
|first3      = M. J.
|last4       = Sumner
|first4      = F. H.
|date        = April 1962
|title       = One-Level Storage System
|journal     = IRE Transactions on Electronic Computers
|issue = 2
|pages = 223–235
|publisher   = Institute of Radio Engineers
|doi = 10.1109/TEC.1962.5219356
}}</ref> to programs.