Editing Phase-change memory (section)

==Challenges==
The greatest challenge for phase-change memory has been the requirement of high programming [[current density]] (>10<sup>7</sup>[[Ampere|&nbsp;A]]/cm<sup>2</sup>, compared to 10<sup>5</sup>...10<sup>6</sup>&nbsp;A/cm<sup>2</sup> for a typical [[transistor]] or [[diode]]). {{citation needed|date=June 2012}}
The contact between the hot phase-change region and the adjacent [[dielectric]] is another fundamental concern. The dielectric may begin to leak [[Electric current|current]] at higher temperature, or may lose [[adhesion]] when expanding at a different rate from the phase-change material.

Phase-change memory is susceptible to a fundamental tradeoff of unintended vs. intended phase-change. This stems primarily from the fact that phase-change is a thermally driven process rather than an electronic process. Thermal conditions that allow for fast [[crystallization]] should not be too similar to standby conditions, e.g. room temperature, otherwise data retention cannot be sustained. With the proper [[activation energy]] for crystallization it is possible to have fast crystallization at programming conditions while having very slow crystallization at normal conditions.

Probably the biggest challenge for phase-change memory is its long-term [[Electrical resistance and conductance|resistance]] and [[threshold voltage]] drift.<ref>{{cite journal |first1=I.V. |last1=Karpov |first2=M. |last2=Mitra |first3=D. |last3=Kau |first4=G. |last4=Spadini |first5=Y.A. |last5=Kryukov |first6=V.G. |last6=Karpov |title=Fundamental drift of parameters in chalcogenide phase change memory |journal=J. Appl. Phys. |volume=102 |issue= 12|pages=124503–124503–6 |year=2007 |doi=10.1063/1.2825650 |bibcode=2007JAP...102l4503K }}</ref> The resistance of the [[Amorphous solid|amorphous]] state slowly increases according to a [[power law]] (~t<sup>0.1</sup>). This severely limits the ability for multilevel operation, since a lower intermediate state would be confused with a higher intermediate state at a later time, and could also jeopardize standard two-state operation if the threshold voltage increases beyond the design value.

In April 2010, [[Numonyx]] released its Omneo line of parallel and serial interface 128&nbsp;Mb [[NOR flash replacement]] PRAM chips. Although the NOR flash chips they intended to replace operated in the −40-85&nbsp;°C range, the PRAM chips operated in the 0-70&nbsp;°C range, indicating a smaller operating window compared to NOR flash. This is likely due to the use of highly temperature-sensitive [[p–n junction]]s to provide the high currents needed for programming.