Editing Watchdog timer (section)

====Digital watchdogs====

In microcontrollers and other complex digital ICs, a digital WDT is typically instantiated by synthesizing it from a description written in [[VHDL]], [[Verilog]] or some other [[hardware description language]]. For example, the following VHDL code describes a simple WDT:

<syntaxhighlight lang="VHDL" class="skin-invert">
entity watchdog_timer is
port (
  CLK      : in  std_logic;             -- clock
  INIT     : in  std_logic;             -- initialize watchdog
  KICK     : in  std_logic;             -- restart timer
  INTERVAL : in  unsigned(31 downto 0); -- timer interval in clocks
  TIMEOUT  : out std_logic;             -- timeout indicator
);
end watchdog_timer;

architecture behavioral of watchdog_timer is
process(CLK)
  variable elapsed : std_logic;              -- timeout register
  variable counter : unsigned(31 downto 0);  -- remaining clocks until timeout
begin
  if rising_edge(CLK) then    -- upon rising clock edge
    if INIT = '1' then        --   if watchdog is being initialized
      counter <= INTERVAL;    --     start timer
      elapsed <= '0';         --     reset timeout indicator
    elsif counter = 0 then    --   else if watchdog interval has elapsed
      elapsed <= '1';         --     indicate timeout; timer is halted
    elsif KICK = '1' then     --   else if watchdog is being kicked
      counter <= INTERVAL;    --     restart timer
    else                      --   else
      counter <= counter - 1; --     advance timer
    end if;
  end if;
  TIMEOUT <= elapsed;  -- send register output to TIMEOUT
end process;
end behavioral;
</syntaxhighlight>