Editing Apollo Guidance Computer (section)

===Data buses===
The AGC had a 16-bit read bus and a 16-bit write bus. Data from central registers (A, Q, Z, or LP), or other internal registers could be gated onto the read bus with a control signal. The read bus connected to the write bus through a non-inverting buffer, so any data appearing on the read bus also appeared on the write bus. Other control signals could copy write bus data back into the registers.

Data transfers worked like this: To move the address of the next instruction from the B register to the S register, an RB (read B) control signal was issued; this caused the address to move from register B to the read bus, and then to the write bus. A WS (write S) control signal moved the address from the write bus into the S register.

Several registers could be read onto the read bus simultaneously. When this occurred, data from each register was inclusive-''OR''ed onto the bus. This inclusive-''OR'' feature was used to implement the Mask instruction, which was a logical ''AND'' operation. Because the AGC had no native ability to do a logical ''AND'', but could do a logical ''OR'' through the bus and could complement (invert) data through the C register, [[De Morgan's laws|De Morgan's theorem]] was used to implement the equivalent of a logical ''AND''. This was accomplished by inverting both operands, performing a logical ''OR'' through the bus, and then inverting the result.