Editing Field-programmable gate array (section)

== Programming ==
{{See|Logic synthesis|Verification and validation|Place and route}}
To define the behavior of the FPGA, the user provides a design in a [[hardware description language]] (HDL) or as a [[schematic]] design. The HDL form is more suited to work with large structures because it's possible to specify high-level functional behavior rather than drawing every piece by hand. However, schematic entry can allow for easier visualization of a design and its [[Modular programming|component modules]].

Using an [[electronic design automation]] tool, a technology-mapped [[netlist]] is generated. The netlist can then be fit to the actual FPGA architecture using a process called ''[[place and route]]'', usually performed by the FPGA company's proprietary place-and-route software. The user will validate the results using [[Static timing analysis|timing analysis]], [[simulation]], and other [[verification and validation]] techniques. Once the design and validation process is complete, the binary file generated, typically using the FPGA vendor's proprietary software, is used to (re-)configure the FPGA. This file is transferred to the FPGA via a [[Serial communication|serial interface]] ([[JTAG]]) or to an external memory device such as an [[EEPROM]].

The most common HDLs are [[VHDL]] and [[Verilog]]. [[National Instruments]]' [[LabVIEW]] graphical programming language (sometimes referred to as ''G'') has an FPGA add-in module available to target and program FPGA hardware. Verilog was created to simplify the process making HDL more robust and flexible. Verilog has a C-like syntax, unlike VHDL.<ref>{{Cite web|title=Battle Over the FPGA: VHDL vs Verilog! Who is the True Champ?|url=https://blog.digilentinc.com/battle-over-the-fpga-vhdl-vs-verilog-who-is-the-true-champ/|access-date=2020-12-16|website=digilentinc.com|language=en-US|archive-date=2020-12-26|archive-url=https://web.archive.org/web/20201226074106/https://blog.digilentinc.com/battle-over-the-fpga-vhdl-vs-verilog-who-is-the-true-champ/|url-status=dead}}</ref>{{sps|{{subst|DATE}}|date=February 2024}}

To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called ''[[Semiconductor intellectual property core|intellectual property (IP) cores]]'', and are available from FPGA vendors and third-party IP suppliers. They are rarely free, and typically released under proprietary licenses. Other predefined circuits are available from developer communities such as [[OpenCores]] (typically released under [[free and open source]] licenses such as the [[GPL]], [[BSD license|BSD]] or similar license). Such designs are known as [[open-source hardware]].

In a typical [[design flow]], an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the [[Register-transfer level|RTL]] description in [[VHDL]] or [[Verilog]] is simulated by creating [[test bench]]es to simulate the system and observe results. Then, after the [[Logic synthesis|synthesis]] engine has mapped the design to a netlist, the netlist is translated to a [[Logic gate|gate-level]] description where simulation is repeated to confirm the synthesis proceeded without errors. Finally, the design is laid out in the FPGA at which point [[propagation delay]] values can be [[Back annotation|back-annotated]] onto the netlist, and the simulation can be run again with these values.

More recently, [[OpenCL]] (Open Computing Language) is being used by programmers to take advantage of the performance and power efficiencies that FPGAs provide. OpenCL allows programmers to develop code in the [[C programming language]].<ref>{{cite web|url=http://streamcomputing.eu/blog/2014-09-16/use-opencl-fpgas/|title=Why use OpenCL on FPGAs?|work=StreamComputing|date=2014-09-16|access-date=2015-07-17|archive-date=2017-01-01|archive-url=https://web.archive.org/web/20170101125857/https://streamcomputing.eu/blog/2014-09-16/use-opencl-fpgas/|url-status=dead}}</ref> For further information, see [[high-level synthesis]] and [[C to HDL]].

Most FPGAs rely on an [[static random-access memory|SRAM]]-based approach to be programmed. These FPGAs are in-system programmable and re-programmable, but require external boot devices. For example, [[flash memory]] or [[EEPROM]] devices may load contents into internal SRAM that controls routing and logic. The SRAM approach is based on [[CMOS]].

Rarer alternatives to the SRAM approach include:
* [[Fuse (electrical)|Fuse]]: one-time programmable. Bipolar. Obsolete.
* [[Antifuse]]: one-time programmable. CMOS. Examples: Actel SX and Axcelerator families; Quicklogic Eclipse II family.<ref name=EDN>{{cite web|url=https://www.edn.com/all-about-fpgas/|title=All about FPGAs|date=21 March 2006 }}</ref>
* [[Programmable read-only memory|PROM]]: programmable read-only memory technology. One-time programmable because of plastic packaging.{{clarify|reason=What's the issue with plastic packages?|date=July 2024}} Obsolete.
* [[EPROM]]: erasable programmable read-only memory technology. One-time programmable but with window, can be erased with ultraviolet (UV) light. CMOS. Obsolete.
* [[EEPROM]]: electrically erasable programmable read-only memory technology. Can be erased, even in plastic packages. Some but not all EEPROM devices can be in-system programmed. CMOS.
* [[Flash memory|Flash]]: flash-erase EPROM technology. Can be erased, even in plastic packages. Some but not all flash devices can be in-system programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is, therefore, less expensive to manufacture. CMOS. Example: Actel ProASIC family.<ref name=EDN/>