Editing Interrupt (section)

==System implementation==
{{POV section|talk=NPOV - PC centric|date=January 2022}}

Interrupts may be fully handled in hardware by the CPU, or may be handled by both the CPU and another component such as a [[programmable interrupt controller]] or a [[southbridge (computing)|southbridge]].

If an additional component is used, that component would be connected between the interrupting device and the processor's interrupt pin to [[multiplexing|multiplex]] several sources of interrupt onto the one or two CPU lines typically available. If implemented as part of the [[memory controller]], interrupts are mapped into the system's memory [[address space]].<!-- Expand on how memory mapped interrupts work. e.g. PowerPC -->{{citation needed|date=November 2023}}

In [[system on a chip|systems on a chip]] (SoC) implementations, interrupts come from different blocks of the chip and are usually aggregated in an interrupt controller attached to one or several processors (in a multi-core system).<ref>{{Citation |last=Yiu |first=Joseph |title=CHAPTER 2 - Overview of the Cortex-M3 |date=2010-01-01 |url=https://www.sciencedirect.com/science/article/pii/B9781856179638000053 |work=The Definitive Guide to the ARM Cortex-M3 (Second Edition) |pages=11–24 |editor-last=Yiu |editor-first=Joseph |access-date=2023-10-11 |place=Oxford |publisher=Newnes |doi=10.1016/b978-1-85617-963-8.00005-3 |isbn=978-1-85617-963-8|url-access=subscription }}</ref>

===Shared IRQs===
{{POV section|date=December 2021}}

Multiple devices may share an edge-triggered interrupt line if they are designed to. The interrupt line must have a pull-down or pull-up resistor so that when not actively driven it settles to its inactive state, which is the default state of it. Devices signal an interrupt by briefly driving the line to its non-default state, and let the line float (do not actively drive it) when not signaling an interrupt. This type of connection is also referred to as [[open collector]]. The line then carries all the pulses generated by all the devices. (This is analogous to the [[pull cord]] on some buses and trolleys that any passenger can pull to signal the driver that they are requesting a stop.) However, interrupt pulses from different devices may merge if they occur close in time. To avoid losing interrupts the CPU must trigger on the trailing edge of the pulse (e.g. the rising edge if the line is pulled up and driven low). After detecting an interrupt the CPU must check all the devices for service requirements.

Edge-triggered interrupts do not suffer the problems that level-triggered interrupts have with sharing. Service of a low-priority device can be postponed arbitrarily, while interrupts from high-priority devices continue to be received and get serviced. If there is a device that the CPU does not know how to service, which may raise spurious interrupts, it will not interfere with interrupt signaling of other devices. However, it is easy for an edge-triggered interrupt to be missed - for example, when interrupts are masked for a period - and unless there is some type of hardware latch that records the event it is impossible to recover. This problem caused many "lockups" in early computer hardware because the processor did not know it was expected to do something. More modern hardware often has one or more interrupt status registers that latch interrupts requests; well-written edge-driven interrupt handling code can check these registers to ensure no events are missed.

The [[Industry Standard Architecture]] (ISA) bus uses edge-triggered interrupts, without mandating that devices be able to share IRQ lines, but all mainstream ISA motherboards include pull-up resistors on their IRQ lines, so well-behaved ISA devices sharing IRQ lines should just work fine. The [[parallel port]] also uses edge-triggered interrupts. Many older devices assume that they have exclusive use of IRQ lines, making it electrically unsafe to share them.

There are three ways multiple devices "sharing the same line" can be raised. First is by exclusive conduction (switching) or exclusive connection (to pins). Next is by bus (all connected to the same line listening): cards on a bus must know when they are to talk and not talk (i.e., the ISA bus). Talking can be triggered in two ways: by accumulation latch or by logic gates. Logic gates expect a continual data flow that is monitored for key signals. Accumulators only trigger when the remote side excites the gate beyond a threshold, thus no negotiated speed is required. Each has its speed versus distance advantages. A trigger, generally, is the method in which excitation is detected: rising edge, falling edge, threshold ([[oscilloscope]] can trigger a wide variety of shapes and conditions).

Triggering for software interrupts must be built into the software (both in OS and app). A 'C' app has a trigger table (a table of functions) in its header, which both the app and OS know of and use appropriately that is not related to hardware. However do not confuse this with hardware interrupts which signal the CPU (the CPU enacts software from a table of functions, similarly to software interrupts).

====Difficulty with sharing interrupt lines====
Multiple devices sharing an interrupt line (of any triggering style) all act as spurious interrupt sources with respect to each other. With many devices on one line, the workload in servicing interrupts grows in proportion to the number of devices. It is therefore preferred to spread devices evenly across the available interrupt lines. Shortage of interrupt lines is a problem in older system designs where the interrupt lines are distinct physical conductors. Message-signaled interrupts, where the interrupt line is virtual, are favored in new system architectures (such as [[PCI Express]]) and relieve this problem to a considerable extent.

Some devices with a poorly designed programming interface provide no way to determine whether they have requested service. They may lock up or otherwise misbehave if serviced when they do not want it. Such devices cannot tolerate spurious interrupts, and so also cannot tolerate sharing an interrupt line. [[Industry Standard Architecture|ISA]] cards, due to often cheap design and construction, are notorious for this problem. Such devices are becoming much rarer, as [[hardware logic]] becomes cheaper and new system architectures mandate shareable interrupts.

===Hybrid===
Some systems use a hybrid of level-triggered and edge-triggered signaling. The hardware not only looks for an edge, but it also verifies that the interrupt signal stays active for a certain period of time.

A common use of a hybrid interrupt is for the NMI (non-maskable interrupt) input. Because NMIs generally signal major – or even catastrophic – system events, a good implementation of this signal tries to ensure that the interrupt is valid by verifying that it remains active for a period of time. This 2-step approach helps to eliminate false interrupts from affecting the system.

===Message-signaled===<!-- This section is linked from [[Interrupt]] -->
{{Main|Message Signaled Interrupts}}

A ''message-signaled interrupt'' does not use a physical interrupt line.  Instead, a device signals its request for service by sending a short message over some communications medium, typically a [[computer bus]]. The message might be of a type reserved for interrupts, or it might be of some pre-existing type such as a memory write.

Message-signalled interrupts behave very much like edge-triggered interrupts, in that the interrupt is a momentary signal rather than a continuous condition.  Interrupt-handling software treats the two in much the same manner. Typically, multiple pending message-signaled interrupts with the same message (the same virtual interrupt line) are allowed to merge, just as closely spaced edge-triggered interrupts can merge.

Message-signalled [[interrupt vector]]s can be shared, to the extent that the underlying communication medium can be shared. No additional effort is required.

Because the identity of the interrupt is indicated by a pattern of data bits, not requiring a separate physical conductor, many more distinct interrupts can be efficiently handled.  This reduces the need for sharing. Interrupt messages can also be passed over a serial bus, not requiring any additional lines.

[[PCI Express]], a serial computer bus, uses [[Message Signaled Interrupts|message-signaled interrupts]] exclusively.

===Doorbell===
{{Unreferenced section|date=December 2020}}
In a [[push button]] analogy applied to [[computer systems]], the term ''doorbell'' or ''doorbell interrupt'' is often used to describe a mechanism whereby a [[software]] system can signal or notify a [[computer hardware]] device that there is some work to be done.  Typically, the software system will place data in some well-known and mutually agreed upon memory locations, and "ring the doorbell" by writing to a different memory location.  This different memory location is often called the doorbell region, and there may even be multiple doorbells serving different purposes in this region. It is this act of writing to the doorbell region of memory that "rings the bell" and notifies the hardware device that the data are ready and waiting.  The hardware device would now know that the data are valid and can be acted upon.  It would typically write the data to a  [[hard disk drive]], or send them over a [[Computer network|network]], or [[encrypt]] them, etc.

The term ''doorbell interrupt'' is usually a [[misnomer]].  It is similar to an interrupt, because it causes some work to be done by the device; however, the doorbell region is sometimes implemented as a [[Polling (computer science)|polled]] region, sometimes the doorbell region writes through to physical device [[Hardware register|registers]], and sometimes the doorbell region is hardwired directly to physical device registers. When either writing through or directly to physical device registers, this may cause a real interrupt to occur at the device's central processor unit ([[CPU]]), if it has one.

Doorbell interrupts can be compared to [[Message Signaled Interrupts]], as they have some similarities.

===Multiprocessor IPI===
In [[multiprocessor]] systems, a processor may send an interrupt request to another processor via [[inter-processor interrupts]]{{efn|Known as shoulder taps on some IBM operating systems.}} (IPI).