Editing Microcode (section)

==Examples==
* The [[Analytical engine]] envisioned by [[Charles Babbage]] uses [[Read-only memory|pegs inserted into rotating drums]] to store its internal procedures.
* The [[EMIDEC 1100]]<ref>{{cite web |url=http://www.emidec.org.uk/ |title=EMIDEC 1100 computer |publisher=Emidec.org.uk |access-date=April 26, 2010 |url-status=live |archive-url=https://web.archive.org/web/20100612184405/http://www.emidec.org.uk/ |archive-date=June 12, 2010}}</ref> reputedly uses a hard-wired control store consisting of wires threaded through ferrite cores, known as "the laces".
* Most models of the IBM System/360 series are microprogrammed:
** The [[IBM System/360 Model 25|Model 25]] is unique among System/360 models in using the top 16&nbsp;K bytes of core storage to hold the control storage for the microprogram. The 2025 uses a 16-bit microarchitecture with seven control words (or microinstructions). After system maintenance or when changing operating mode, the microcode is loaded from the card reader, tape, or other device.<ref>{{cite book |title=IBM System/360 Model 25 Functional Characteristics |date=January 1968 |publisher=IBM |id=A24-3510-0 |page=22 |url=http://www.bitsavers.org/pdf/ibm/360/functional_characteristics/A24-3510-0_360-25_funcChar_Jan68.pdf |access-date=October 29, 2021}}</ref> The [[IBM 1410]] emulation for this model is loaded this way.
** The [[IBM 2030|Model 30]] uses an 8-bit microarchitecture with only a few hardware registers; everything that the programmer saw is emulated by the microprogram. The microcode for this model is also held on special punched cards, which are stored inside the machine in a dedicated reader per card, called "CROS" units (Capacitor Read-Only Storage).<ref name="360-30-feto">{{cite book |url=http://www.bitsavers.org/pdf/ibm/360/fe/2030/Y24-3360-1_2030_FE_Theory_Opns_Jun67.pdf |title=Field Engineering Theory of Operation, 2030 Processing Unit, System/360 Model 30 |edition=First |date=June 1967 |publisher=IBM |id=Y24-3360-1 |access-date=2019-11-09 |url-status=live |archive-url=https://web.archive.org/web/20200401215647/http://www.bitsavers.org/pdf/ibm/360/fe/2030/Y24-3360-1_2030_FE_Theory_Opns_Jun67.pdf |archive-date=2020-04-01}}</ref>{{rp|2–5}} Another CROS unit is added for machines ordered with 1401/1440/1460 emulation<ref name="360-30-feto"/>{{rp|4–29}} and for machines ordered with 1620 emulation.<ref name="360-30-feto"/>{{rp|4–75}}
** The [[IBM System/360 Model 40|Model 40]] uses 56-bit control words. The 2040 box implements both the System/360 main processor and the multiplex channel (the I/O processor). This model uses ''TROS'' dedicated readers similar to ''CROS'' units, but with an inductive pickup (Transformer Read-only Store).
** The [[IBM System/360 Model 50|Model 50]] has two internal datapaths which operated in parallel: a 32-bit datapath used for arithmetic operations, and an 8-bit data path used in some logical operations. The control store uses 90-bit microinstructions.
** The [[IBM System/360 Model 85|Model 85]] has separate instruction fetch (I-unit) and execution (E-unit) to provide high performance. The I-unit is hardware controlled. The E-unit is microprogrammed; the control words are 108 bits wide on a basic 360/85 and wider if an emulator feature is installed.
* The [[NCR 315]] is microprogrammed with hand wired ferrite cores (a [[Read-only memory|ROM]]) pulsed by a sequencer with conditional execution. Wires routed through the cores are enabled for various data and logic elements in the processor.
* The Digital Equipment Corporation [[PDP-9]] processor, KL10 and KS10 [[PDP-10]] processors, and [[PDP-11]] processors with the exception of the PDP-11/20, are microprogrammed.<ref>{{cite book|url=https://archive.org/details/computerstructur01siew/page/671|chapter-url=http://gordonbell.azurewebsites.net/computer_structures_principles_and_examples/csp0687.htm|editor1=Daniel P. Siewiorek|editor-link1=Daniel Siewiorek|editor2=C. Gordon Bell|editor-link2=Gordon Bell|editor3=Allen Newell|editor-link3=Allen Newell|title=Computer Structures: Principles and Examples|chapter=Implementation and Performance Evaluation of the PDP-11 Family|author1=Edward A. Snow|author2=Daniel P. Siewiorek|page=[https://archive.org/details/computerstructur01siew/page/671 671]|publisher=[[McGraw-Hill|McGraw-Hill Book Company]]|location=[[New York, NY]]|year=1982|isbn=0-07-057302-6|url-access=registration}}</ref>
* Most [[Data General Eclipse]] minicomputers are microprogrammed. The task of writing microcode for the [[Data General Eclipse MV/8000|Eclipse MV/8000]] is detailed in the Pulitzer Prize-winning book titled ''[[The Soul of a New Machine]]''.
* Many systems from [[Burroughs Corporation|Burroughs]] are microprogrammed:
:* The B700 "microprocessor" execute application-level opcodes using sequences of 16-bit microinstructions stored in main memory; each of these is either a register-load operation or mapped to a single 56-bit "nanocode" instruction stored in read-only memory. This allows comparatively simple hardware to act either as a mainframe peripheral controller or to be packaged as a standalone computer.
:* The [[B1700]] is implemented with radically different hardware including bit-addressable main memory but has a similar multi-layer organisation. The operating system preloads the interpreter for whatever language is required. These interpreters present different virtual machines for [[COBOL]], [[Fortran]], etc.
* [[Microdata Corporation|Microdata]] produced computers in which the microcode is accessible to the user; this allows the creation of custom assembler level instructions. Microdata's [[Pick operating system|Reality]] operating system design makes extensive use of this capability.
* The [[Xerox Alto#Architecture|Xerox Alto]] workstation used a microcoded design but, unlike many computers, the microcode engine is not hidden from the programmer in a layered design. Applications take advantage of this to accelerate performance.
* The [[IBM System/38]] is described as having both [[IBM System/38#Microcode|horizontal and vertical microcode]].<ref>{{cite journal|url=https://www.computer.org/csdl/magazine/co/1981/09/01667517/13rRUwciPii|title=Design of a Small Business Data Processing System|first=Frank|last=Soltis|journal=[[IEEE Computer]]|date=September 1981|volume=14|pages=77–93|doi=10.1109/C-M.1981.220610|s2cid=398484|url-access=subscription}}</ref> In practice, the processor implements an instruction set architecture named the ''Internal Microprogrammed Interface'' (IMPI) using a horizontal microcode format. The so-called vertical microcode layer implements the System/38's hardware-independent [[IBM System/38#Machine Interface|Machine Interface]] (MI) instruction set by translating MI code to IMPI code and executing it. Prior to the introduction of the [[IBM RS64]] processor line, early [[IBM AS/400]] systems used the same architecture.<ref name="inside-as400">{{cite book|title=Inside the AS/400, Second Edition|url=https://books.google.com/books?id=5DoPAAAACAAJ|isbn=978-1882419661|author=Frank G. Soltis|year=1997|publisher=Duke Press}}</ref> 
* The [[Nintendo 64]]'s [[Reality Coprocessor]] (RCP), which serves as the console's [[graphics processing unit]] and audio processor, utilizes microcode; it is possible to implement new effects or tweak the processor to achieve the desired output. Some notable examples of custom RCP microcode include the high-resolution graphics, particle engines, and unlimited draw distances found in [[Factor 5]]'s ''[[Indiana Jones and the Infernal Machine]]'', ''[[Star Wars: Rogue Squadron]]'', and ''[[Star Wars: Battle for Naboo]]'';<ref name="Interview: Battling the N64 (Naboo)">{{cite web |url=http://ign64.ign.com/articles/087/087646p1.html |title=Interview: Battling the N64 (Naboo) |publisher=IGN64 |date=November 10, 2000 |access-date=March 27, 2008 |url-status=live |archive-url=https://web.archive.org/web/20070913180626/http://ign64.ign.com/articles/087/087646p1.html |archive-date=September 13, 2007}}</ref><ref name="Indiana Jones and the Infernal Machine">{{cite web |title=Indiana Jones and the Infernal Machine |website=IGN |url=http://www.ign.com/articles/2000/12/13/indiana-jones-and-the-infernal-machine-2 |date=December 12, 2000 |access-date=September 24, 2013 |url-status=live |archive-url=https://web.archive.org/web/20130927083807/http://www.ign.com/articles/2000/12/13/indiana-jones-and-the-infernal-machine-2 |archive-date=September 27, 2013}}</ref> and the [[full motion video]] playback found in [[Rockstar San Diego|Angel Studios]]' ''[[Resident Evil 2]]''.<ref name="Postmortem RE2 N64">{{cite news |last=Meynink |first=Todd |date=July 28, 2000 |url=http://www.gamasutra.com/view/feature/3148/postmortem_angel_studios_.php |title=Postmortem: Angel Studios' Resident Evil 2 (N64 Version) |work=[[Gamasutra]] |publisher=[[United Business Media|United Business Media LLC]] |access-date=October 18, 2010 |url-status=dead |archive-url=https://web.archive.org/web/20121021070818/http://www.gamasutra.com/view/feature/3148/postmortem_angel_studios_.php |archive-date=October 21, 2012}}</ref>
{{Further|topic=Nintendo 64 microcode|Nintendo 64 programming characteristics|Nintendo 64 Game Pak}}
* The VU0 and VU1 vector units in the [[Sony]] [[PlayStation 2]] are microprogrammable; in fact, VU1 is only accessible via microcode for the first several generations of the SDK.
* The MicroCore Labs [http://www.microcorelabs.com/mcl86.html MCL86] {{Webarchive|url=https://web.archive.org/web/20161103224205/http://www.microcorelabs.com/mcl86.html |date=2016-11-03 }} , [http://www.microcorelabs.com/mcl51.html MCL51] {{Webarchive|url=https://web.archive.org/web/20170202042033/http://www.microcorelabs.com/mcl51.html |date=2017-02-02 }} and [http://www.microcorelabs.com/mcl65.html MCL65] {{Webarchive|url=https://web.archive.org/web/20181221000146/http://www.microcorelabs.com/mcl65.html |date=2018-12-21 }} are examples of highly encoded "vertical" microsequencer implementations of the Intel 8086/8088, 8051, and MOS 6502.
* The [http://www.bitsavers.org/pdf/digitalScientific/ Digital Scientific Corp.] Meta 4 Series 16 computer system was a user-microprogammable system first available in 1970. The microcode had a primarily vertical style with 32-bit microinstructions.<ref>{{cite book |url=http://www.bitsavers.org/pdf/digitalScientific/7032MO_Meta4Series16RefMan.pdf |title=Digital Scientific Meta 4 Series 16 Computer System Reference Manual |id=7032MO |publisher=Digital Scientific Corporation |date=May 1971 |access-date=2020-01-14 |url-status=live |archive-url=https://web.archive.org/web/20200114014526/http://www.bitsavers.org/pdf/digitalScientific/7032MO_Meta4Series16RefMan.pdf |archive-date=2020-01-14}}</ref> The instructions were stored on replaceable program boards with a grid of bit positions. One (1) bits were represented by small metal squares that were sensed by amplifiers, zero (0) bits by the absence of the squares.<ref>{{cite book |url=http://www.bitsavers.org/pdf/digitalScientific/7024MO_ROMmanual_Mar70.pdf|title=Digital Scientific Meta 4 Computer System Read-Only Memory (ROM) Reference Manual |id=7024MO |publisher=Digital Scientific Corporation |date=March 1970 |access-date=2020-01-14 |url-status=live |archive-url=https://web.archive.org/web/20190923061816/http://bitsavers.org/pdf/digitalScientific/7024MO_ROMmanual_Mar70.pdf |archive-date=2019-09-23}}</ref> The system could be configured with up to 4K 16-bit words of microstore. One of Digital Scientific's products was an emulator for the [[IBM 1130]].<ref>{{cite book |url=http://www.bitsavers.org/pdf/digitalScientific/7006MO_Meta16_SysMan_Jun70.pdf |title=The Digital Scientific Meta 4 Series 16 Computer System Preliminary System Manual |id=7006MO |publisher=Digital Scientific Corporation |date=June 1970 |access-date=2020-01-14 |url-status=live |archive-url=https://web.archive.org/web/20190923061755/http://bitsavers.org/pdf/digitalScientific/7006MO_Meta16_SysMan_Jun70.pdf |archive-date=2019-09-23}}</ref><ref>{{cite book |url=http://www.bitsavers.org/pdf/digitalScientific/M4-005P-170_1130rom_Jan70.pdf |title=Digital Scientific Meta 4 Computer System Typical ROM Pattern Listing and Program To Simulate The IBM 1130 Instruction Set |id=M4/005P-170 |publisher=Digital Scientific Corporation |date=January 1970 |access-date=2020-01-14 |url-status=live |archive-url=https://web.archive.org/web/20200324115023/http://bitsavers.org/pdf/digitalScientific/M4-005P-170_1130rom_Jan70.pdf |archive-date=2020-03-24}}</ref>
* The [[MCP-1600]] is a [[microprocessor]] made by [[Western Digital]] from 1975 through the early 1980s. It was used to implement three different computer architectures in microcode: the [[Pascal MicroEngine]], the [[WD16]], and the [[Digital Equipment Corporation|DEC]] [[PDP-11#LSI-11|LSI-11]], a cost-reduced PDP-11.<ref>{{cite web |url=http://www.antiquetech.com/?page_id=782 |title=Western Digital 1600 |publisher=AntiqueTech |access-date=5 January 2017 |url-status=dead |archive-url=https://web.archive.org/web/20170103021205/http://www.antiquetech.com/?page_id=782 |archive-date=3 January 2017}}</ref>
* Earlier [[x86]] processors are fully microcoded. x86 processors implemented [[patchable microcode]] (patch by [[BIOS]] or [[operating system]]) since [[P6 (microarchitecture)|Intel P6 microarchitecture]] and [[Athlon|AMD K7 microarchitecture]]. Such processors implemented microcode ROM and microcode SRAM in their silicon.
* Many [[video card]]s and [[network interface controller]]s implement patchable microcode (patch by operating system). Such microcode is patched to device's [[Static random-access memory|SRAM]] or [[DRAM]], for example, [[GDDR SDRAM]] of a video card.