Editing Single-photon avalanche diode (section)

==== IC fabrication improvements ====
With the advancement of [[Three-dimensional integrated circuit|3D IC technologies]], i.e. stacking of integrated circuits, the fill factor could be enhanced further by allowing the top die to be optimised for a high fill-factor SPAD array, and the lower die for readout circuits and signal processing.<ref>{{Cite journal|s2cid=21729101|date=2018|title=High-Performance Back-Illuminated Three-Dimensional Stacked Single-Photon Avalanche Diode Implemented in 45-nm CMOS Technology|journal=IEEE Journal of Selected Topics in Quantum Electronics|volume=24|issue=6|page=2827669|doi=10.1109/JSTQE.2018.2827669|bibcode=2018IJSTQ..2427669L|url=http://infoscience.epfl.ch/record/256438/files/High-Performance%20Back-Illuminated%20Three-Dimensional%20Stacked%20Single-Photon%20Avalanche%20Diode%20Implemented%20in%2045-nm%20CMOS%20Technology.pdf|last1=Lee|first1=Myung-Jae|last2=Ximenes|first2=Augusto Ronchini|last3=Padmanabhan|first3=Preethi|last4=Wang|first4=Tzu-Jui|last5=Huang|first5=Kuo-Chin|last6=Yamashita|first6=Yuichiro|last7=Yaung|first7=Dun-Nian|last8=Charbon|first8=Edoardo|doi-access=free}}</ref> As small dimension, high-speed processes for transistors may require different optimisations than optically sensitive diodes, 3D-ICs allow the layers to be separately optimised.