Editing MIPS architecture (section)

== Application-specific extensions ==

The base MIPS32 and MIPS64 architectures can be supplemented with a number of optional architectural extensions, which are collectively referred to as ''application-specific extensions'' (ASEs). These ASEs provide features that improve the efficiency and performance of certain workloads, such as [[digital signal processing]].

=== MIPS MCU ===
Enhancements for microcontroller applications. The MCU ASE (application-specific extension) has been developed to extend the [[interrupt]] controller support, reduce the interrupt latency and enhance the I/O peripheral control function typically required in microcontroller system designs.
* Separate priority and vector generation
* Supports up to 256 interrupts in EIC (External Interrupt Controller) mode and eight hardware interrupt pins
* Provides 16-bit vector offset address
* Pre-fetching of the interrupt exception vector
* Automated Interrupt Prologue – adds hardware to save and update system status before the interrupt handling routine
* Automated Interrupt Epilogue – restores the system state previously stored in the stack for returning from the interrupt.
* Interrupt Chaining – supports the service of pending interrupts without the need to exit the initial interrupt routine, saving the cycles required to store and restore multiple active interrupts
* Supports speculative pre-fetching of the interrupt vector address. Reduces the number of interrupt service cycles by overlapping memory accesses with pipeline flushes and exception prioritization
* Includes atomic bit set/clear instructions which enables bits within an I/O register that are normally used to monitor or control external peripheral functions to be modified without interruption, ensuring the action is performed securely.

=== MIPS16 ===
MIPS16 is an Application-Specific Extension for MIPS I through to V designed by [[LSI Logic]] and [[MIPS Technologies]], announced on October 21, 1996, alongside its first implementation, the LSI Logic TinyRISC processor.<ref>{{cite press release |title=Silicon Graphics Introduces Compact MIPS RISC Microprocessor Code For High Performance at a Low Cost |date=October 21, 1996}}</ref> MIPS16 was subsequently licensed by [[NEC Electronics]], [[Philips Semiconductors]], and [[Toshiba]] (among others); and implemented as an extension to the MIPS I, II, an III architectures. MIPS16 decreases the size of application by up to 40% by using 16-bit instructions instead of 32-bit instructions and also improves power efficiency, the instruction cache hit rate, and is equivalent in performance to its base architecture.<ref>{{cite book|last1=Sweetman|first1=Dominic|title=See MIPS Run|date=2007|publisher=Morgan Kaufmann Publishers|location=San Francisco, California|isbn=978-0-12-088421-6|pages=425–427|edition=2nd}}</ref> It is supported by hardware and software development tools from MIPS Technologies and other providers. MIPS16e is an improved version of MIPS16 first supported by MIPS32 and MIPS64 Release 1. MIPS16e2 is an improved version of MIPS16 that is supported by MIPS32 and MIPS64 (up to Release 5). Release 6 replaced it with microMIPS.

=== MIPS Digital Signal Processing (DSP) ===
The DSP ASE is an optional extension to the MIPS32/MIPS64 Release&nbsp;2 and newer instruction sets which can be used to accelerate a large range of "media" computations—particularly audio and video. The DSP module comprises a set of instructions and state in the integer pipeline and requires minimal additional logic to implement in MIPS processor cores. Revision 2 of the ASE was introduced in the second half of 2006. This revision adds extra instructions to the original ASE, but is otherwise backwards-compatible with it.<ref>{{cite web|url=https://gcc.gnu.org/onlinedocs/gcc/MIPS-DSP-Built-in-Functions.html|title=Using the GNU Compiler Collection (GCC): MIPS DSP Built-in Functions|website=gcc.gnu.org|url-status=live|archive-url=https://web.archive.org/web/20170420143138/https://gcc.gnu.org/onlinedocs/gcc/MIPS-DSP-Built-in-Functions.html|archive-date=April 20, 2017}}</ref> Unlike the bulk of the MIPS architecture, it's a fairly irregular set of operations, many chosen for a particular relevance to some key algorithm. Its main novel features (vs original MIPS32):<ref>{{cite web|url=https://www.linux-mips.org/wiki/Instruction_Set_Architecture#DSP_ASE|title=Instruction Set Architecture - LinuxMIPS|website=www.linux-mips.org|url-status=dead|archive-url=https://web.archive.org/web/20170420045837/https://www.linux-mips.org/wiki/Instruction_Set_Architecture#DSP_ASE|archive-date=April 20, 2017}}</ref>
* Saturating arithmetic (when a calculation overflows, deliver the representable number closest to the non-overflowed answer).
* Fixed-point arithmetic on signed 32- and 16-bit fixed-point fractions with a range of -1 to +1 (these are widely called "Q31" and "Q15").
* The existing integer multiplication and multiply-accumulate instructions, which deliver results into a double-size accumulator (called "hi/lo" and 64 bits on MIPS32 CPUs). The DSP ASE adds three more accumulators, and some different flavours of multiply-accumulate.
* [[Single instruction, multiple data|SIMD]] instructions operating on 4 x unsigned bytes or 2 x 16-bit values packed into a 32-bit register (the 64-bit variant of the DSP ASE supports larger vectors, too).
* SIMD operations are basic arithmetic, shifts and some multiply-accumulate type operations.

=== MIPS SIMD architecture (MSA) ===
Instruction set extensions designed to accelerate multimedia.
* 32 vector registers of 16 x 8-bit, 8 x 16-bit, 4 x 32-bit, and 2 x 64 bit vector elements
* Efficient vector parallel arithmetic operations on integer, fixed-point and floating-point data
* Operations on absolute value operands
* Rounding and saturation options available
* Full precision multiply and multiply-add
* Conversions between integer, floating-point, and fixed-point data
* Complete set of vector-level compare and branch instructions with no condition flag
* Vector (1D) and array (2D) shuffle operations
* Typed load and store instructions for [[Endianness|endian]]-independent operation
* IEEE Standard for Floating-Point Arithmetic 754-2008 compliant
* Element precise floating-point exception signaling
* Pre-defined scalable extensions for chips with more gates/transistors
* Accelerates compute-intensive applications in conjunction with leveraging generic compiler support
* Software-programmable solution for consumer electronics applications or functions not covered by dedicated hardware
* Emerging data mining, feature extraction, image and video processing, and human-computer interaction applications
* High-performance scientific computing

=== MIPS virtualization ===
Hardware supported virtualization technology.

=== MIPS multi-threading ===
Each multi-threaded MIPS core can support up to two VPEs (Virtual Processing Elements) which share a single pipeline as well as other hardware resources. However, since each VPE includes a complete copy of the processor state as seen by the software system, each VPE appears as a complete standalone processor to an [[Symmetric multiprocessing|SMP]] Linux operating system. For more fine-grained thread processing applications, each VPE is capable of supporting up to nine TCs allocated across two VPEs. The TCs share a common execution unit but each has its own program counter and core register files so that each can handle a thread from the software. The MIPS MT architecture also allows the allocation of processor cycles to threads, and sets the relative thread priorities with an optional Quality of Service ([[Quality of service|QoS]]) manager block. This enables two prioritization mechanisms that determine the flow of information across the bus. The first mechanism allows the user to prioritize one thread over another. The second mechanism is used to allocate a specified ratio of the cycles to specific threads over time. The combined use of both mechanisms allows effective allocation of bandwidth to the set of threads, and better control of latencies. In real-time systems, system-level determinism is very critical, and the QoS block facilitates improvement of the predictability of a system. Hardware designers of advanced systems may replace the standard QoS block provided by MIPS Technologies with one that is specifically tuned for their application.

=== SmartMIPS ===
SmartMIPS is an Application-Specific Extension (ASE) designed by [[Gemplus International]] and MIPS Technologies to improve performance and reduce memory consumption for [[smart card]] software. It is supported by MIPS32 only, since smart cards do not require the capabilities of MIPS64 processors. Few smart cards use SmartMIPS.

=== [[MDMX|MIPS Digital Media eXtension]] (MDMX) ===
Multimedia application accelerations that were common in the 1990s on RISC and CISC systems. 

=== [[MIPS-3D]] ===
Additional instructions for improving the performance of 3D graphics applications