Editing Random-access machine (section)

== Turing equivalence of the RAM with indirection ==
In the section above we informally showed that a RAM with an unbounded indirection capability produces a [[Post–Turing machine]]. The Post–Turing machine is Turing equivalent, so we have shown that the RAM with indirection is Turing equivalent.

We give here a slightly more formal demonstration. Begin by designing our model with three reserved registers "E", "P", and "N", plus an unbounded set of registers 1, 2, ..., n to the right. The registers 1, 2, ..., n will be considered "the squares of the tape". Register "N" points to "the scanned square" that "the head" is currently observing. The "head" can be thought of as being in the conditional jump{{spaced ndash}}observe that it uses indirect addressing (cf Elgot-Robinson p.&nbsp;398). As we decrement or increment "N" the (apparent) head will "move left" or "right" along the squares. We will move the contents of "E"=0 or "P"=1 to the "scanned square" as pointed to by N, using the indirect CPY.

The fact that our tape is left-ended presents us with a minor problem: Whenever LEFT occurs our instructions will have to test to determine whether or not the contents of "N" is zero; if so we should leave its count at "0" (this is our choice as designers{{spaced ndash}}for example we might have the machine/model "trigger an event" of our choosing).

:Instruction set 1 (augmented): { INC (N), DEC (N), CLR (N), CPY (d, r<sub>s</sub>,i, N), JZ ( i, r, z ), HALT }

The following table both defines the Post-Turing instructions in terms of their RAM equivalent instructions and gives an example of their functioning. The (apparent)location of the head along the tape of registers r0-r5 . . . is shown shaded:
{|class="toccolours"
|-  style="text-align:left; font-size:9pt; vertical-align:bottom; background:lavender;"
!  style="width:51.6; font-weight:bold; height:12px;"| Mnemonic
!  style="font-weight:bold; width:60px;"| label:
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| style="width:4.8;"|
!  style="font-weight:bold; width:16.2;"| E
!  style="font-weight:bold; width:16.2;"| P
!  style="font-weight:bold; width:16.2;"| N
!  style="font-weight:bold; width:4.8;"|
!  style="font-weight:bold; width:14.4;"| r0
!  style="font-weight:bold; width:14.4;"| r1
!  style="font-weight:bold; width:14.4;"| r2
!  style="font-weight:bold; width:14.4;"| r3
!  style="font-weight:bold; width:14.4;"| r4
!  style="font-weight:bold; width:14.4;"| r5
!  style="font-weight:bold; width:22.8;"| etc.
!  style="font-weight:bold; width:84px;"| Action on registers
!  style="font-weight:bold; width:229.2;"| Action on finite-state machine Instruction Register IR
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|-  style="font-size:9pt; vertical-align:top;"
|  style="text-align:left; height:9.6; "| R
|  style="text-align:left; font-style:Italic; "| right:
| style="text-align:left;" | INC ( N )
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|  style="text-align:left; color:#969696; "| 0
|  style="text-align:left; color:#969696; "| 1
|  style="text-align:left; font-weight:bold; "| 4
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|  style="text-align:left; "| [N] +1 → N
|  style="text-align:left; "| [IR] +1 → IR
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|  style="text-align:left; height:9.6; "| P
|  style="text-align:left; font-style:Italic; "| print:
| style="text-align:left;" | CPY ( d, P, i, N )
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|  style="text-align:left; font-weight:bold; color:#969696; "| 0
|  style="text-align:left; font-weight:bold; "| 1
|  style="text-align:left; color:#969696; "| 4
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|  style="text-align:left; "| [P]=1 → [N]=r4
|  style="text-align:left; "| [IR] +1 → IR
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|  style="text-align:left; height:9.6; "| E
|  style="text-align:left; font-style:Italic; "| erase:
| style="text-align:left;" | CPY ( d, E, i, N )
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|  style="text-align:left; font-weight:bold; "| 0
|  style="text-align:left; color:#969696; "| 1
|  style="text-align:left; font-weight:bold; "| 4
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|  style="text-align:left; "| [E]=0 → [N]=r4
|  style="text-align:left; "| [IR] +1 → IR
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|-  style="font-size:9pt; vertical-align:top;"
|  style="text-align:left; height:9.6; "| L
|  style="text-align:left; font-style:Italic; "| left:
| style="text-align:left;" | JZ ( i, N, end )
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|  style="text-align:left; "| 0
|  style="text-align:left; color:#969696; "| 1
|  style="text-align:left; font-weight:bold; "| 4
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|  style="text-align:left; "| IF [[N]] =r4] =0 THEN "end" → IR else [IR]+1 → IR
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| style="text-align:left;" | DEC ( N )
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|  style="text-align:left; "| [N] -1 → N
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|-  style="font-size:9pt; vertical-align:top;"
|  style="text-align:left; height:9.6; "| J0 ( halt )
|  style="text-align:left; font-style:Italic; "| jump_if_blank:
| style="text-align:left;" | JZ ( i, N, end )
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|  style="text-align:left; "| IF N =r3] =0 THEN "end" → IR else [IR]+1 → IR
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|-  style="font-size:9pt; vertical-align:top;"
|  style="text-align:left; height:9.6; "| J1 ( halt )
|  style="text-align:left; font-style:Italic; "| jump_if_mark:
| style="text-align:left;" | JZ ( i, N, halt )
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|  style="text-align:left; "| 0
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|  style="text-align:left; font-weight:bold; "| 3
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|  style="text-align:left; "| N =r3] → A
|  style="text-align:left; "| IF N =r3] =0 THEN "end" → IR else [IR]+1 → IR
|-  style="font-size:9pt; vertical-align:top;"
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|  style="text-align:left; font-style:Italic; "| end
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|style="font-style:Italic" | halt:
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